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Teacher
Teacher
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Registered: ‎07-09-2009

warning, [Synth 8-5827] expecting unsigned expression

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I have a warning in vivado 2016.1 on a generate loop,

 

address_top is defined as a std_logic_vector, as is Bank_Decode,

   should just decode to a bunch of small rom / luts.

 

Why does vivado expect an unsigned ?


-- Set the which bank decode for use later
G_0 : for i in 0 to 15 generate
Bank_decode( i ) <= '1' when address_top = std_logic_vector( to_unsigned( i, address_top'length )) else '0';
end generate G_0;

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Teacher
Teacher
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Registered: ‎03-31-2012

Re: warning, [Synth 8-5827] expecting unsigned expression

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>>  and 'length is also an unsigned integer, again as far as I know.

 

 

1076 says 'length return type is integer. Functionally it returns a non-negative value but the type is integer.

to_unsigned expects a 'natural' for its second operand so the warning is legitimate as far as VHDL type checking is concerned. You are supplying a value of integer type to a location which wants a natural type ie 0..M.

 

Try casting the return of 'length to unsigned before using it and see if it helps.

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Teacher
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Registered: ‎07-09-2009

Re: warning, [Synth 8-5827] expecting unsigned expression

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any one any thoughts ?

 

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Teacher
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Registered: ‎03-31-2012

Re: warning, [Synth 8-5827] expecting unsigned expression

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1) why does this bother you?
2) which function gives the warning? is it for the second operand of the to_unsigned? 'length returns integer, maybe to_unsigned expects second operand to be unsigned?
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Teacher
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Registered: ‎07-09-2009

Re: warning, [Synth 8-5827] expecting unsigned expression

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in revers order,

 

2) yes its the to_ that is in error

 

1) why does this bother me ?  

       a) why,  dont warnings bother you ?

       b) some of my clients need all warnings identified as to cause as part of sign off

       c) it has worked on all previous version of vhdl tools, why has it stopped ?

               is it a change in the xilinx tools ( a mistake or correcting a mistake ) or  

                     change in the vhdl standard ?

  

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Teacher
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Re: warning, [Synth 8-5827] expecting unsigned expression

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2) to_unsigned parameters are natural ie non-negative. But length returns integer so these are incompatible types. It's possible that Xilinx tools have become more compliant. Technically you can't assign integer to natural without possibility of loss.

1.a) when I program I do it with -Wall and try to clean-up everything. Alas RTL tools are not advanced enough to accomplish this (IMNSHO). Sometimes, they confuse INFO with WARNING and I have enough white hairs on my head already.
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Teacher
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Registered: ‎07-09-2009

Re: warning, [Synth 8-5827] expecting unsigned expression

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in the loop, the to_unsigned , the first paramiter is the lop count , i

 

loop counts in vhdl are deinfed as unsigned integer as far as I know,

   and 'length is also an unsigned integer, again as far as I know.

 

so to_unsigned( i, 8) should return the value of i, as an 8 bit unsifned, which is then cast to std_logic_vector.

 

Also this pass's in model sim when it was running a few years ago, yes its old code ,  withotu probem,

 

also works withotu warngin under ISE and vivado up to and including 2015.4, not 2016.1..

 

strange, ether 2016.1 is wornlg or the other programs are wrong, 

   which one ?

 

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Teacher
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Registered: ‎03-31-2012

Re: warning, [Synth 8-5827] expecting unsigned expression

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>>  and 'length is also an unsigned integer, again as far as I know.

 

 

1076 says 'length return type is integer. Functionally it returns a non-negative value but the type is integer.

to_unsigned expects a 'natural' for its second operand so the warning is legitimate as far as VHDL type checking is concerned. You are supplying a value of integer type to a location which wants a natural type ie 0..M.

 

Try casting the return of 'length to unsigned before using it and see if it helps.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Teacher
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Registered: ‎07-09-2009

Re: warning, [Synth 8-5827] expecting unsigned expression

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thanks

 

I cn go for that as an explanation,

 

sounds like I need to update my code a bit, and ++marks for 2016.1 for getting that test right.

 

 

 

 

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Newbie
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Registered: ‎03-26-2018

Re: warning, [Synth 8-5827] expecting unsigned expression

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This issue stil persists in version 2017.3  I get it for this synthexis warning:

 

[Synth 8-5825] expecting unsigned expression

 

for this line of code

 

if adc_signed_17bit < to_signed(-32768,17) then

 

Can I ignore the warning?

 

ben

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: warning, [Synth 8-5827] expecting unsigned expression

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what binary value are you expecting for -32768 ?

 

 

And I'd expect you to start a new thread please, not grab this closed one,.

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