warnings after transfer code from Spartan 6 to Spartan 3E

[chennan]

Hi all,

I did a project on Spartan 6 before and want to transfer it to Spartan 3E this time. So I changed the device setting and ucf of the old file. The simulation resutl doesn't change after this device setting change. However, I got strange warnings (see below) which didn't show before and the I/O output doesn't work the way as simulation indicates after downloading to the FPGA. 

Here is the module with problem.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:08:21 07/31/2013
// Design Name:
// Module Name: SlaveMotor
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SlaveMotor(clk,limit,drivemotor,ratio,motordrive
);
input clk;
input [1:0] limit;
input [1:0] drivemotor; //The drive signal of the master step motor, bit 1 control direction, bit 2 control step
input [7:0] ratio;
output [1:0] motordrive; //The output signal to control the slave step motor

reg [1:0] motordrive;
initial motordrive<=2'b00;

//Debouncer for limit
reg [1:0] Dlimit;
reg [1:0] Midlimit;
reg [15:0] Dcnt;
initial Dcnt=0;
always @ (posedge clk)
begin
Midlimit<=limit;
if (Midlimit==limit) Dcnt<=Dcnt+1;
else Dcnt<=0;
if (Dcnt>=6000)
begin
Dlimit<=Midlimit;
Dcnt<=0;
end
end

//Read the limit sensor output and decide the direction of the motion
reg direction; //Use to indicate the main motion direction
initial direction=0;
reg LlimitDelay;
initial LlimitDelay=0;
reg RlimitDelay;
initial RlimitDelay=0;
always @ (posedge clk)
begin
LlimitDelay<=Dlimit[0];
RlimitDelay<=Dlimit[1];
if ((~LlimitDelay)&&Dlimit[0]) direction<=~direction; //motordrive control the direction of the motor
else if ((~RlimitDelay)&&Dlimit[1]) direction<=~direction;
end
/////////////////////////////////////////////////////////////////////////

//Use ratio and the control of the driver motor to give pulse of the slave motor
parameter signed [8:0] upper_cnt=60; //Use this ratio to test the system, could be replaced by ratio(input) in the future,64-4 to give some tolerance on fiber diameter
parameter signed [8:0] lower_cnt=-60;
reg signed [8:0] cnt;
initial cnt=0;
always @ (posedge drivemotor[0])
begin
if (direction)
begin
if (drivemotor[1]) cnt<=cnt+1;
else cnt<=cnt-1;
end
else begin
if (~drivemotor[1]) cnt<=cnt+1;
else cnt<=cnt-1;
end
if (cnt>=upper_cnt/2) //Divided by 2 because only use the posedge of drivemotor
begin
motordrive[0]<=~motordrive[0];
if (LlimitDelay&&Dlimit[0]) motordrive[1]<=1;
else if (RlimitDelay&&Dlimit[1]) motordrive[1]<=0;
else motordrive[1]<=1;
cnt<=0;
end
if (cnt<=lower_cnt/2)
begin
motordrive[0]<=~motordrive[0];
if (LlimitDelay&&Dlimit[0]) motordrive[1]<=1;
else if (RlimitDelay&&Dlimit[1]) motordrive[1]<=0;
else motordrive[1]<=0;
cnt<=0;
end
end

endmodule

And here is the warnings, the 2677 warnings which didn't show before with Spartan 6 are the cause of all problems I believe. However I don't understand why these warning appear.

WARNING:ProjectMgmt - File C:/Users/ChennanLab/Xilinx/Spartan 3E project/Stepperwithencoder/Stepperwithencoder_map.ncd is missing.
WARNING:Xst:852 - "Stepperwithencoder.v" line 62: Unconnected input port 'ratio' of instance 'uSlaveMotor' is tied to GND.
WARNING:Xst:1305 - Output <overflow> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <ratio> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <setsteps> is used but never assigned. This sourceless signal will be automatically connected to value 000000000010011100010000.
WARNING:Xst:2677 - Node <direction> of sequential type is unconnected in block <SlaveMotor>.
WARNING:Xst:2677 - Node <Dlimit_1> of sequential type is unconnected in block <SlaveMotor>.
WARNING:Xst:2677 - Node <RlimitDelay> of sequential type is unconnected in block <SlaveMotor>.
WARNING:Xst:2677 - Node <cnt_0> of sequential type is unconnected in block <SlaveMotor>.
WARNING:Xst:2677 - Node <cnt_1> of sequential type is unconnected in block <SlaveMotor>.
WARNING:Xst:2677 - Node <cnt_2> of sequential type is unconnected in block <SlaveMotor>.
WARNING:Xst:2677 - Node <cnt_3> of sequential type is unconnected in block <SlaveMotor>.
WARNING:Xst:2677 - Node <cnt_4> of sequential type is unconnected in block <SlaveMotor>.
WARNING:Xst:2677 - Node <cnt_5> of sequential type is unconnected in block <SlaveMotor>.
WARNING:Xst:2677 - Node <cnt_6> of sequential type is unconnected in block <SlaveMotor>.
WARNING:Xst:2677 - Node <cnt_7> of sequential type is unconnected in block <SlaveMotor>.
WARNING:Xst:2677 - Node <cnt_8> of sequential type is unconnected in block <SlaveMotor>.
WARNING:ProjectMgmt - File C:/Users/ChennanLab/Xilinx/Spartan 3E project/Stepperwithencoder/Stepperwithencoder_map.ncd is missing.
WARNING:ProjectMgmt - File C:/Users/ChennanLab/Xilinx/Spartan 3E project/Stepperwithencoder/Stepperwithencoder_map.ncd is missing.
WARNING:ProjectMgmt - File C:/Users/ChennanLab/Xilinx/Spartan 3E project/Stepperwithencoder/Stepperwithencoder_map.ncd is missing.
WARNING:ProjectMgmt - File C:/Users/ChennanLab/Xilinx/Spartan 3E project/Stepperwithencoder/Stepperwithencoder_map.ncd is missing.

Thanks in advance!

Chennan

[vemulad · Accepted solution]

Hi,

Looks like the synthesis ( old parser) is trimming the design.
Did you run post synthesis simulation? Are you not seeing expected results?

The spartan 3e device uses old parser for synthesis and spartan 6 uses new parser. For spartan 3e project you can enable the use of new parser switch using -use_new_parser switch. Check this thread http://forums.xilinx.com/t5/Synthesis/DAVIDN-OVERLOAD-Overloaded-load-65535-lt-0-000000-max-value-is/m-p/376057#M9369

Try using new parser to see same results as that of spartan 6.

Thanks,
Deepika.

[chennan]

Hi Deepika,

Thank you for your help. I am working on it.

Best,

Chennan

[chennan]

I tried the new parser and the problem is solved for this part of the project.
Thank you very much! I should post this thread two days ago:)

[gszakacs]

I played around with this for a while and found that the old parser removed the input signal drivemotor[1].  I tried to understand why, but it didn't make sense.  Looking at the RTL schematic I found a number of dashed lines which seem to correspond to removed logic, but again no clear reason.  It might make sense for Xilinx to look into this because the old parsers are clearly messing up.

On another note, the comparison "if (Midlimit==limit)" can fail if limit is not synchronous to the clk.  However that wouldn't explain why synthesis messed up.  It could only indicate why the design might have intermittent issues in detecting a change in the limit input.

[siktap]

Moving this to Synthesis board

[chennan]

Hi,
I found that the cause for the mes up is"if (cnt>=upper_cnt/2)" and "if (cnt<=lower_cnt/2)". It now seems to me that the old parser doesn't support this kind of syntax. Problem can also be solved byu changing these two expressions to "if (cnt>=upper_cnt)" and "if (cnt<=lower_cnt)" with the old parser.
Best,
Chennan