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Anonymous
Not applicable
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what is the difference?

Hi, I have the following two type of codes. Infact the difference is not significant(input signal 'V2' is used instead of 'Rotate' signal in the first code) , however the utilization values after synthesis are quite different. The second code occupies at least four times more space than the first code

 

======================= 1. CODE=======================

entity deneme is
    Generic (
        IW                                : integer := 8;
        L                                : integer := 8
    );
    Port (
        clk                                : in  std_logic;
       
        V                                : in  std_logic;
        V2                                : in  std_logic;
        I                                : in  std_logic_vector(IW-1 downto 0);
        Q                                : in  std_logic_vector(IW-1 downto 0);
       
        Io                                : out std_logic_vector(IW-1 downto 0);
        Qo                                : out std_logic_vector(IW-1 downto 0)
    );
end deneme;
   
architecture Behavioral of deneme is   
    type type_1_a is array (L-1 downto 0) of std_logic_vector(IW-1 downto 0);
    signal dl_I_1                        : type_1_a := (others => (others => '0'));
    signal dl_Q_1                        : type_1_a := (others => (others => '0'));

    signal dl_I_2                        : type_1_a := (others => (others => '0'));
    signal dl_Q_2                        : type_1_a := (others => (others => '0'));
   
    signal Rotate                        : std_logic := '0';
begin
    process(clk)
    begin
        if rising_edge(clk) then
            Rotate <= not Rotate;
               
            if V = '1' then
                dl_I_1(0) <= I;
                dl_Q_1(0) <= Q;
               
                dl_I_1(L-1 downto 1) <= dl_I_1(L-2 downto 0);
                dl_Q_1(L-1 downto 1) <= dl_Q_1(L-2 downto 0);
               
                dl_I_2(0) <= dl_I_1(L-1);
                dl_Q_2(0) <= dl_Q_1(L-1);
               
                dl_I_2(L-1 downto 1) <= dl_I_2(L-2 downto 0);
                dl_Q_2(L-1 downto 1) <= dl_Q_2(L-2 downto 0);
            elsif V2 = '1' then
                dl_I_1(0) <= dl_I_1(L-1);
                dl_Q_1(0) <= dl_Q_1(L-1);
               
                dl_I_1(L-1 downto 1) <= dl_I_1(L-2 downto 0);
                dl_Q_1(L-1 downto 1) <= dl_Q_1(L-2 downto 0);
               
                dl_I_2(0) <= dl_I_2(L-1);
                dl_Q_2(0) <= dl_Q_2(L-1);   
               
                dl_I_2(L-1 downto 1) <= dl_I_2(L-2 downto 0);
                dl_Q_2(L-1 downto 1) <= dl_Q_2(L-2 downto 0);
            end if;
            Io <= dl_I_2(L-1);
            Qo <= dl_Q_2(L-1);
        end if;
    end process;

end Behavioral;

======================= 2. CODE======================= 

entity deneme is
    Generic (
        IW                                : integer := 8;
        L                                : integer := 8
    );
    Port (
        clk                                : in  std_logic;
       
        V                                : in  std_logic;
        V2                                : in  std_logic;
        I                                : in  std_logic_vector(IW-1 downto 0);
        Q                                : in  std_logic_vector(IW-1 downto 0);
       
        Io                                : out std_logic_vector(IW-1 downto 0);
        Qo                                : out std_logic_vector(IW-1 downto 0)
    );
end deneme;
   
architecture Behavioral of deneme is   
    type type_1_a is array (L-1 downto 0) of std_logic_vector(IW-1 downto 0);
    signal dl_I_1                        : type_1_a := (others => (others => '0'));
    signal dl_Q_1                        : type_1_a := (others => (others => '0'));

    signal dl_I_2                        : type_1_a := (others => (others => '0'));
    signal dl_Q_2                        : type_1_a := (others => (others => '0'));
   
    signal Rotate                        : std_logic := '0';
begin
    process(clk)
    begin
        if rising_edge(clk) then
            Rotate <= not Rotate;
               
            if V = '1' then
                dl_I_1(0) <= I;
                dl_Q_1(0) <= Q;
               
                dl_I_1(L-1 downto 1) <= dl_I_1(L-2 downto 0);
                dl_Q_1(L-1 downto 1) <= dl_Q_1(L-2 downto 0);
               
                dl_I_2(0) <= dl_I_1(L-1);
                dl_Q_2(0) <= dl_Q_1(L-1);
               
                dl_I_2(L-1 downto 1) <= dl_I_2(L-2 downto 0);
                dl_Q_2(L-1 downto 1) <= dl_Q_2(L-2 downto 0);
            elsif Rotate = '1' then
                dl_I_1(0) <= dl_I_1(L-1);
                dl_Q_1(0) <= dl_Q_1(L-1);
               
                dl_I_1(L-1 downto 1) <= dl_I_1(L-2 downto 0);
                dl_Q_1(L-1 downto 1) <= dl_Q_1(L-2 downto 0);
               
                dl_I_2(0) <= dl_I_2(L-1);
                dl_Q_2(0) <= dl_Q_2(L-1);   
               
                dl_I_2(L-1 downto 1) <= dl_I_2(L-2 downto 0);
                dl_Q_2(L-1 downto 1) <= dl_Q_2(L-2 downto 0);
            end if;
            Io <= dl_I_2(L-1);
            Qo <= dl_Q_2(L-1);
        end if;
    end process;

end Behavioral;

 

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6 Replies
Highlighted
Professor
Professor
5,948 Views
Registered: ‎08-14-2007

Re: what is the difference?

Since the difference in your code is essentially nothing, I would suggest looking

at the instantiation.  For example if V2 stays zero in operation, the two

codes would differ in that only the Code 2 using Rotate could ever reach

the elsif portion.  If this is the case, Code 1 could be simplified greatly

and it may even be able to use SRL's for the shift registers.

-- Gabor
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Highlighted
Voyager
Voyager
5,944 Views
Registered: ‎08-30-2007

Re: what is the difference?

Have you looked at your synthesis (.syr) report?  It should show you what logic was infered and what

was optimised away.  This might give you some hints as to what is going on.

 

John Providenza

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Highlighted
Anonymous
Not applicable
5,939 Views

Re: what is the difference?

I am selecting this module as the top module, so ISE does not know whether V2 is always zero or not. It is just an input
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Anonymous
Not applicable
5,938 Views

Re: what is the difference?

I also check the RTL Schematic, they are same
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Highlighted
Professor
Professor
5,922 Views
Registered: ‎08-14-2007

Re: what is the difference?

How did you determine the difference in size?  Is it in the map report?
-- Gabor
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Highlighted
Anonymous
Not applicable
5,890 Views

Re: what is the difference?

yes of course. I compare the number  of used LUT's after the mapping
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