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Explorer
Explorer
2,620 Views
Registered: ‎12-22-2010

what this code mean

hi
    type  state_type     is (amp_state, adc_state);
    type  amp_state_type is (amp_s1, amp_s2, amp_s3,amp_s4);
    type  adc_state_type is (adc_s1, adc_s2,adc_s3,adc_s4);
    -----------------------------------------------
    signal state: state_type:= amp_state;
    signal amp_state_reg    : amp_state_type := amp_s1;
    signal adc_state_reg    : adc_state_type := adc_s1;

 

best regards

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Teacher
Teacher
2,618 Views
Registered: ‎03-31-2012

Re: what this code mean

This is called enumerated type. If you are familiar with C/C++ the same thing can be accomplished by using enum and typdef constructs.

This code is declaring 3 types (state, amp and adc) which have specific values they can take. Then 3 signals of those types are declared. So the signal state can take values of amp_state and adc_state only. The synthesizer is free to assign any physical value to these signals. One may imagine state being a single bit variable with values 0 and 1 or two bits with value 01 and 10 or any other assignment. This is one nice thing about VHDL where enumerated types are built in to the language.
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Moderator
Moderator
2,596 Views
Registered: ‎04-17-2011

Re: what this code mean

Recommended: Read 3.1.1 of VHDL-LRM for enumeration type.
Regards,
Debraj
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