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Visitor
Visitor
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Registered: ‎10-06-2016

which is better? rst= VCC or rst= '1'

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 hi

any difference that i use rst= VCC or rst= '1' (in the following code) ? 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.std_logic_unsigned.ALL; 


entity seg_top is

	generic(Crystal_Value:integer:=50000000);		
	Port ( 	
				rst,GCLK	   :	in	std_logic;
				sel	           :	out	std_logic_vector(3 downto 0);
				leds		   :	out	std_logic_vector(0 to 7)
	      );

end seg_top;

architecture Behavioral of seg_top is

signal	VCC		        :	std_logic;
signal	Number 			:	integer range 0 to 9:=0;
	
	------------------------------------------
	--										
	--	Definition of ROM type for	
	--	7-Seg Display				
	--										
	------------------------------------------
type ROM is array (0 to 9) of std_logic_vector(0 to 7);
signal Seven_Segment : ROM:=(
			      x"fc",x"60",x"da",x"f2",x"66",
			      x"b6",x"be",x"e0",x"fe",x"e6");
							
begin

	VCC			<= '1';
	sel 			<= "0001";		--To select First 7segment for ever
	leds			<= Seven_Segment( Number );

process(GCLK,rst)
variable ctr: integer range 0 to Crystal_Value-1;
begin
	if rst= VCC then
		ctr:=0;
		Number <= 0;
	elsif rising_edge(GCLK) then
		if ctr < Crystal_Value - 1 then
			ctr:=ctr+1;
		else
			ctr:=0;
			if Number<9 then
				Number<=Number+1;
			else
				Number <= 0;
			end if;	
		end if;
	end if;
end process;

end Behavioral;
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Teacher
Teacher
5,441 Views
Registered: ‎03-31-2012

Re: which is better? rst= VCC or rst= '1'

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no difference as far as either simulation or synthesis is concerned. There is no reason to use VCC either. It would just be confusing. rst = 1 is perfectly fine.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Highlighted
Visitor
Visitor
3,002 Views
Registered: ‎10-06-2016

Re: which is better? rst= VCC or rst= '1'

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any difference that i use rst= VCC or rst= '1' (in the following code) ?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity uart is
		Port ( 
					clk 		   	: in	std_logic;
					RX_Pin			: in	std_logic;
					TX_Pin			: out	std_logic
		      );
end uart;

architecture simple of uart is

signal	TX_Reg		    	      :	std_logic_vector(7 downto 0);
signal	GND,VCC				      :	std_logic;
signal	Wr_En,Wr_En_D1,NewData	  :	std_logic;


signal	OneBit_Time_Reg		   :	integer range 0 to 5208;
signal	HalfBit_Time_Reg	   :	integer range 0 to 2604;

type	Uart_TX_Phase is (
							Standby,Start_Bit_TX,Data_TX,
							Stop_Bit_TX
						  );	
signal	TX_State			:	Uart_TX_Phase;	


type	Uart_RX_Phase is (
							Standby,Start_Bit_RX,Data_RX,
							Stop_Bit_RX
						  );	
signal	RX_State		:	Uart_RX_Phase;	

signal	RX_Reg		    :	std_logic_vector(7 downto 0);


begin

	 GND <= '0';
	 VCC <= '1';

			------------------------------------------
			--										
			--		Baud Rate Management Control	
			--										
			------------------------------------------
	
  	 OneBit_Time_Reg 	<= 5208;	--50000000Hz/9600 Bps	
	 HalfBit_Time_Reg	<= 2604;	


		------------------------------------------												
		--			Transmission Sequences											
		------------------------------------------
recieve:process (clk)
variable bit_ctr		: integer range 0 to 7;	
variable Baud_Ctr	    : integer range 0 to 5208;
begin

	if rising_edge(clk) then
		case RX_State is	
----------		StandBy Mode, Ready to start Async Transmission 	
			when Standby	=>
				Wr_En			<= VCC;
				if RX_Pin = GND then
					RX_State		<= Start_Bit_RX;	
				end if;									
----------		First State receiving Satrt Bit which is 0		-----
			when Start_Bit_RX	=>
				if Baud_Ctr < HalfBit_Time_Reg then
					Baud_Ctr	:=Baud_Ctr+1;
				else
					Baud_Ctr:=0;
					if RX_Pin = GND then	--  the Start bit is gotten correctly
						RX_State			<= Data_RX;	
					else
						RX_State		    <= Standby;	--wrong start bit condition it neglects it
					end if;
				end if;	
----------		Second State which is sending Data Byte		-----
			when Data_RX	=>
				if Baud_Ctr < OneBit_Time_Reg then
					Baud_Ctr	:= Baud_Ctr+1;
				else
					RX_Reg(bit_ctr) <= RX_Pin; 
					Baud_Ctr:=0;
-----------------------------------------------------------------
					if bit_ctr<7 then
						bit_ctr:=bit_ctr+1;
					else
						bit_ctr:=0;
						RX_State <= Stop_Bit_RX;
					end if;
				end if;	
------------------		End of Sending The Byte				--------
-----------------------------------------------------------------
----------		Receiving The stop bit 	(it is not check the stop bit[s])
-----------------------------------------------------------------
			when Stop_Bit_RX	=>
			  
						
				if Baud_Ctr < OneBit_Time_Reg then
					  Baud_Ctr	:=Baud_Ctr+1;
					  elsif RX_Pin = GND then
					      RX_State		<= Standby;
					  else
							Baud_Ctr		:=0;
							RX_State 	<= Standby;
							Wr_En			<= GND;
							TX_Reg		<= RX_Reg;
				end if;						
-----------------------------------------------------------------
			when others =>
				null;
-----------------------------------------------------------------
		end case;	
	end if;
end process;


transmit:process (clk)
variable bit_ctr	: integer range 0 to 7;	
variable Baud_Ctr	: integer range 0 to 5208;
begin

	if rising_edge(clk) then
		
		Wr_En_D1 <= Wr_En;						 --Detection of Low egde of Wr_En signal
		if Wr_En='0' and  Wr_En_D1='1' then
			NewData <= '1';
		end if;

		case TX_State is	
----------		StandBy Mode, Ready to start Async Transmission 	
			when Standby	=>
				TX_Pin	<= VCC;
				if NewData = '1' then 
					NewData <= '0';
					TX_State <= Start_Bit_TX;	-- starts sending data
				end if;									
----------		First State Sending Satrt Bit which is 0		-----
			when Start_Bit_TX	=>
				if Baud_Ctr < OneBit_Time_Reg then
					Baud_Ctr	:=Baud_Ctr+1;
					TX_Pin	<= GND; 
				else
					Baud_Ctr:=0;
					TX_State <= Data_TX;
				end if;	
----------		Second State which is sending Data Byte		-----
			when Data_TX	=>
				if Baud_Ctr < OneBit_Time_Reg then
					Baud_Ctr	:=Baud_Ctr+1;
					TX_Pin		<= TX_Reg(bit_ctr); 
				else
					if bit_ctr < 7 then
						bit_ctr := bit_ctr + 1;
					else
						bit_ctr:=0;
						TX_State <= Stop_Bit_TX;
					end if;
					Baud_Ctr	:=0;
				end if;	
----------------		End of Sending The Byte				--------
-----------------------------------------------------------
----------		 		sending The stop bit 			--------
-----------------------------------------------------------
			when Stop_Bit_TX	=>
				if Baud_Ctr < OneBit_Time_Reg then
					Baud_Ctr	:=Baud_Ctr+1;
					TX_Pin	<= VCC; 
				else
					Baud_Ctr	:=0;
					TX_State <= Standby;
				end if;	

-----------------------------------------------------------------
			when others =>
				null;
-----------------------------------------------------------------
		end case;	
	end if;

end process;

end simple;
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Highlighted
Teacher
Teacher
5,442 Views
Registered: ‎03-31-2012

Re: which is better? rst= VCC or rst= '1'

Jump to solution
no difference as far as either simulation or synthesis is concerned. There is no reason to use VCC either. It would just be confusing. rst = 1 is perfectly fine.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

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Moderator
Moderator
2,960 Views
Registered: ‎07-21-2014

Re: which is better? rst= VCC or rst= '1'

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@fpgaamoz

 

I don't think so there will be any difference. Tool will synthesize the logic in the same manner. 

 

Thanks,
Anusheel
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Highlighted
Visitor
Visitor
2,953 Views
Registered: ‎10-06-2016

Re: which is better? rst= VCC or rst= '1'

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thank you very much.

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