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Visitor
908 Views
Registered: ‎05-31-2018

## why this FSM verilog code doesn't work properly

I wrote this code for an FSM design that lets the user to enter the input A, displays what he entered, then lets him to enter the input B, displays it, then displays the sum of A and B. you can see the FSM here

for the code I wrote it by Verilog and tested by Basys 3 board. Firstly I tested the FA code alone to check if it works fine, and it does, the problem when I tested the FSM code, it doesn't really work as I expects, it seems there's problem with the denouncing button btnC, because the sequences of the states after I tried many times are not the same.

here is my code:

````timescale 1ns / 1ps

input [15:0] sw //switches,
input clk,
input btnC,btnU //push buttons,
output reg [15:0] led,
output reg [6:0] seg,
output reg [3:0] an,
output dp
);
reg [3:0] dn; //displayed number
wire cin; // first carry in (zero)
reg[2:0] cn; //internal carry-ins
reg [3:0]A,B; //user data inputs
reg [2:0] y,Y; //p-s , n-s
parameter [2:0] a=0,b=1,c=2,d=3,e=4; //states

task bit; //to calculate the sum of a single bit.
input a; //first number
input b; //second number
input cin; //carry in
output s; //sum
output cout; //cout
reg w1, w2, w3;
begin
w1=a&&b;
w2=a&&cin;
w3=b&&cin;
cout=w1||w2||w3;
s=a^b^cin;
end

reg timer,rtimer;
reg btnc,flag;
initial begin rtimer = {20{1'b1}}; end
always@(posedge clk) begin //debouncing btnC

if(btnc!=btnC)  begin
timer<=0; btnc<=btnC; flag<=0; end
else if(timer>=rtimer)
flag=1;
else timer=timer+1;
end
always@(*) begin //saving the value of A
case(y)
b: A=sw[3:0];
endcase
end
always@(*) begin //saving the value of B
case(y)
d: B=sw[3:0];
endcase
end

always@(*) led[3:0]=sw[3:0];

always@(*) begin
case(y) //displays the letter "A"
a: begin
an=4'b0111;
dn=10;
if(btnc&&flag)
Y=b;
else
Y=a;
end
b: begin //the user enters the value of A, the seven segment display displays it.
an=4'b1110;
dn=sw[3:0];
if(btnc&&flag)
Y=c;
else
Y=b;
end
c: begin //displays the letter "b".
an=4'b0111;
dn=11;
if(btnc&&flag)
Y=d;
else
Y=c;
end
d: begin //the user enters the value of B, and the seven segment display displays it.
dn=sw[3:0];
an=4'b1110;
if(btnc&&flag)
Y=e;
else
Y=d;
end
e: begin //caculate the sum and displays it.
an=4'b1110;
bit(A[0],B[0],cin,dn[0],cn[0]);
bit(A[1],B[1],cn[0],dn[1],cn[1]);
bit(A[2],B[2],cn[1],dn[2],cn[2]);
bit(A[3],B[3],cn[2],dn[3],led[15]);
if(btnc&&flag)
Y=a;
else
Y=e;
end

endcase
end

always@(posedge clk)begin
if(btnU) //resert
y<=a;
else
y<=Y;
end

always@(dn) begin //
case(dn)
0: seg= 7'b1000000; // "0"
1: seg= 7'b1111001; // "1"
2: seg= 7'b0100100; // "2"
3: seg= 7'b0110000; // "3"
4: seg= 7'b0011001; // "4"
5: seg= 7'b0010010; // "5"
6: seg= 7'b0000010; // "6"
7: seg= 7'b1111000; // "7"
8: seg= 7'b0000000; // "8"
9: seg= 7'b0010000; // "9"
10:seg= 7'b0001000; // "a"
11:seg= 7'b0000011; // "b"
12:seg= 7'b0000110; // "c"
13:seg= 7'b0100001; // "d"
14:seg= 7'b0000110;
15:seg= 7'b0001110;
default: seg = 7'b0000001; // "0"
endcase
end
endmodule

```

Tags (4)
3 Replies
Moderator
769 Views
Registered: ‎11-09-2015

## Re: why this FSM verilog code doesn't work properly

HI @mmmtgoo,

Did you run any simulation with you FSM?

Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Visitor
766 Views
Registered: ‎05-31-2018

## Re: why this FSM verilog code doesn't work properly

Yes I did, no errors.
Moderator
755 Views
Registered: ‎11-09-2015

## Re: why this FSM verilog code doesn't work properly

HI @mmmtgoo,

This is a pushbutton, you might want to try to sample its state multiple time (ex on 3 clocks) to make sure the level is correct

Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**