works in testbench, not on the board(Spartan 3A starter kit)

[lakshnar]

The problem is some signals are not getting reset at the required time, I have NO errors or warnings in my code. 

Code structure :

signal x : STD_LOGIC:= '0';

begin

process(clk,all signals)

VARIABLE T_delay  : integer range 0 to 2000000000;

begin

if(clk'event and clk = '1') then

if(( A = '0') and (B = '0') )

if(signal_x = '1')

if(T_delay  < 200000000) 

--Begin a loop and stay with K='1' and F='0' for a few seconds

K <='1';

F <='0'

T_delay  = T_delay +1;

else 

--Loop is over and stay at K='0' and F='1' until further change in input

K <= '0';

F <= '1';

T_d := 1;

 x  <= '0' ;

end if;

else

-- incase signal x = 0

K <= '0';

F <= '0';

T_d := 1;

 x  <= '0' ;

endif;

elsif(( A = '0') and (B = '1') )

K <= '1';

F <= '1';

T_d := 1;

 x  <= '1' ;

elsif(( A = '1') and (B = '1') )

K <= '0' ;

F <= '0' ;

T_d := 1;

 x  <= '0' ;

else

K <= '0' ;

F <= '0' ;

T_d := 1;

 x  <= '0' ;

end if;

end if;

So we can see that the signal x must store the value 1 in a particular state and this is used to create an output in another state. i,e , IF : A = 0 and B = 1 and immediately A = 0 and B = 0, then the loop with T_d begins because x stored '1' from the previous state. For other states such at A = 1 and B= 1 and A = 1 and B = 0 x is supposed to be set to 0.

My problem is - for the first few tries, everything works fine, the algorithm works fine, then suddenly this loop with T_delay seems to run when ever A= 0 and B=0 irrespective of the previous states. I believe x is not getting reset to 0. 

My code works perfectly fine on the Xilinx VHDL testbench.

in my ucf I used the NET "A" CLOCK_DEDICATED_ROUTE = FALSE; I and settled some Physical design rules error 372 warnings with the "if(clk'event and clk = '1') " statements..

Where could the problem be?

[austin]

The warnings,

Dedicated clock routing (use of BUFG) is absoluterly required for large counters.

I am surprised it 'works' at all,

[lakshnar]

What i have presented here is only a sample of the logic, just to demonstrate the kind of erratic behavior observed. The statement CLOCK_DEDICATED_ROUTE = FALSE; had been suggested by the compiler and now there are NO warnings or errors. However, the erratic behavior remains.

Regards,

Narender

[muzaffer]

how is signal_x being set? is it an external event ? If so you need to synchronize it with the clk clock.

[gszakacs]

---

@lakshnar wrote:
What i have presented here is only a sample of the logic, just to demonstrate the kind of erratic behavior observed. The statement CLOCK_DEDICATED_ROUTE = FALSE; had been suggested by the compiler and now there are NO warnings or errors. However, the erratic behavior remains.

Regards,

Narender

---

Perhaps if you attach the actual logic we could suggest a fix.  As it stands there are too many problems with the example code you posted for it to possibly synthesize.

[lakshnar]

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 09:11:01 11/26/2014

-- Design Name:

-- Module Name: RCDC_WARSTEIN_1 - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity RCDC_WARSTEIN_1 is

Port ( clk : in STD_LOGIC;

M_in : in STD_LOGIC;

Vce_RC : in STD_LOGIC;

Vce_L : in STD_LOGIC;

Z : in STD_LOGIC;

Reset : in STD_LOGIC;

LWL3 : out STD_LOGIC;

LWL2 : out STD_LOGIC;

LWL1 : out STD_LOGIC);

end RCDC_WARSTEIN_1;

architecture Behavioral of RCDC_WARSTEIN_1 is

--constant T_interlock : time := 11000 ns; -- Time for Interlock period

--constant T_desat : time := 10000 ns; -- Time for desaturation period

signal Diode_Mode_1, Diode_Mode_2 , IGBT_Mode , Desat_Done : STD_LOGIC ;

signal Do_desat : STD_LOGIC:= '0';

signal FLR : STD_LOGIC:= '0';

signal T_interlock : integer := 0;

--signal T_intL : integer := 2200;

signal T_SC : integer := 0;

signal EN_desat : STD_LOGIC:= '0';

--signal T_desat : integer ;

--signal T_dst : integer := 2000;

--signal SC : integer := 500;--- Equivalent of 2.5 µS

begin

EN_desat <= (not M_in) and (Do_desat) and (not Desat_Done) and (not Diode_Mode_1) and (not Diode_Mode_2) and (not IGBT_Mode) and (not Vce_RC);

process(clk,FLR,M_in,Do_desat,Vce_RC,T_SC,Desat_Done,Diode_Mode_1,Diode_Mode_2,IGBT_Mode,Vce_L,Z,T_interlock,Reset,EN_desat)

--

VARIABLE T_desat : integer range 0 to 2000000000;

begin

if(clk'event and clk = '1') then

-----------FLR----------------------------------------------------------------------------

if ( FLR = '0') then

if((Vce_RC = '1') and (M_in = '0') and (Do_desat = '1') and (Desat_Done = '0') and (Diode_Mode_1 = '0') and (Diode_Mode_2 = '0') and (IGBT_Mode = '0')) then

--!!!-x-Short Circuit Loop- 2.5µS(500 clock cycles @100MHZ)-x-!!!--

if(T_SC < 200000000) then T_SC <= T_SC + 1;

FLR <= '0';

else

--Vge : -15V using Rg Nominal(OFF)

--Emitter is connected to +15V Bus

LWL3 <= '0';

LWL2 <= '0';

LWL1 <= '0';

FLR <= '1';------FLR Remains ON in '1' until 'Reset' happens

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

IGBT_Mode <= '0';

Desat_Done <= '0';

T_desat := 1 ;

--T_SC <= 0 ;

end if;

--!!!--SC Loop---------------

end if;

--------------------------------When FLR = 0---------------------------------

if(EN_desat = '1') then

if(T_desat < 200000000) then T_desat := T_desat+1;

--Vge : +15V using RgD. Begining of Desat process

LWL3 <= '1';

LWL2 <= '1';

LWL1 <= '0';

--Emitter connected to ground bus

--Do_desat <= '1';

-- Desat process completed, now the system is kept in

---OFF state with RgD_OFF = 1

--and Desat_Done=1.

else

--Vge : -15V using RgD

LWL3 <= '1';

LWL2 <= '0';

LWL1 <= '0';

--Emitter connected to +15V Bus

FLR <= '0';

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

IGBT_Mode <= '0';

Desat_Done <= '1';

--Variable ensures continuity in Vge : -15V using RgD when µC = 0

T_desat := 1 ;

Do_desat <= '0';

end if;

elsif (( M_in = '0') and (Do_desat = '0')) then --When the Opto coupler/µC pulse is no longer available---------------

T_SC <= 0 ;

T_interlock <= 0;

if ((Desat_Done = '1')) then

--Let the system remain in OFF state with RgD_OFF

--Vge : -15V using RgD

--Emitter connected to +15V Bus

LWL3 <= '1';

LWL2 <= '0';

LWL1 <= '0';

Do_desat <= '0';

FLR <= '0';

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

IGBT_Mode <= '0';

Desat_Done <= '1';

--Variable ensures continuity in Vge : -15V using RgD when µC = 0

--T_interlock <= 0;

elsif ((Diode_Mode_1 = '1')) then

-- Turn OFF in diode mode requires the completion of the desat

---process

--Vge : +15V using RgD. Begining of Desat process

LWL3 <= '1';

LWL2 <= '1';

LWL1 <= '0';

Do_desat <= '1';

--T_desat <= T_desat+1;

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

elsif ((Diode_Mode_2 = '1')) then

-- Turn OFF in diode mode requires the completion of the desat

---process

--Vge : +15V using RgD. Begining of Desat process

LWL3 <= '1';

LWL2 <= '1';

LWL1 <= '0';

Do_desat <= '1';

--T_desat <= T_desat+1;

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

else

-- Turn off using RgN_OFF

--Vge : -15V using Rg Nominal(OFF)

--Emitter is connected to +15V Bus

LWL3 <= '0';

LWL2 <= '0';

LWL1 <= '0';

FLR <= '0';

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

IGBT_Mode <= '0';

Desat_Done <= '0';

T_desat := 1 ;

end if;

-----Conditions for Opto/µC pulse = 0 completed-----

elsif((M_in = '1')) then

----Begin : When the Opto coupler/µC pulse is available-------------

Do_desat <= '0';

T_desat := 1 ;

if (IGBT_Mode = '1') then

---++When IGBT Mode is already active+++++

if(Vce_L = '0') then

T_SC <= 0 ;

if( Z = '0') then

--Vge : -15V using RgD. Transition into Diode_Mode

--from IGBT_Mode

LWL3 <= '1';

LWL2 <= '0';

LWL1 <= '0';

FLR <= '0';

Diode_Mode_2 <= '1';

--Variable is set to Diode_Mode

Diode_Mode_1 <= '0';

IGBT_Mode <= '0';

--IGBT_Mode is removed

Desat_Done <= '0';

else

--Vge : 0V using RgD_ON and RgN_ON. Transition into

--Diode_Mode from IGBT_Mode

LWL3 <= '1';

LWL2 <= '1';

LWL1 <= '1';

FLR <= '0';

Diode_Mode_2 <= '1';

--Variable is set to Diode_Mode

Diode_Mode_1 <= '0';

IGBT_Mode <= '0';

--IGBT_Mode is removed

Desat_Done <= '0';

end if;

else

--Vge : +15V using RgNominal(ON)

--Emitter connected to the GND bus

LWL3 <= '0';

LWL2 <= '1';

LWL1 <= '0';

FLR <= '0';

Diode_Mode_2 <= '0';

Do_desat <= '0';

Diode_Mode_1 <= '0';

IGBT_Mode <= '1';

--IGBT_Mode is maintained

Desat_Done <= '0';

end if;

if(Vce_RC = '1') then

--!!!-x-Short Circuit Loop- 2.5µS

--(500 clock cycles @100MHZ)-x-!!!--

if(T_SC < 200000000) then T_SC <= T_SC + 1;

FLR <= '0';

else

--Vge : -15V using Rg Nominal(OFF)

--Emitter is connected to +15V Bus

LWL3 <= '0';

LWL2 <= '0';

LWL1 <= '0';

FLR <= '1';

--FLR Remains ON in '1' until 'Reset' happens

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

IGBT_Mode <= '0';

Desat_Done <= '0';

T_desat := 1 ;

--T_SC <= 0 ;

end if;

--!!!--SC Loop---------------

end if;

---+++++++++++IGBT Mode is no longer active+++++++++++

elsif(Diode_Mode_1 = '1') then

T_interlock <= 0;

T_SC<= 0;

---When Diode Mode is active->---Diode_Mode--

---Diode_Mode--Diode_Mode -

--Diode_Mode--Diode_Mode---

if( Vce_RC = '1') then

--Vge : +15V using RgNominal(ON)

--Emitter connected to the GND bus

LWL3 <= '0';

LWL2 <= '1';

LWL1 <= '0';

FLR <= '0';

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

IGBT_Mode <= '1';--IGBT_Mode is turned on

Desat_Done <= '0';

Do_desat <= '0';

elsif((Vce_RC = '0') and (Vce_L = '1')) then

Diode_Mode_1 <= '1';

Diode_Mode_2 <= '0';

if( Z = '0') then

--Vge : -15V using RgD. Transition into Diode_Mode from IGBT_Mode

LWL3 <= '1';

LWL2 <= '0';

LWL1 <= '0';

FLR <= '0';

Diode_Mode_1 <= '1';

Diode_Mode_2 <= '0';

IGBT_Mode <= '0';--IGBT_Mode is removed

Desat_Done <= '0';

else

--Vge : 0V using RgD_OFF and RgN_OFF. Transition into Diode_Mode from IGBT_Mode

LWL3 <= '1';

LWL2 <= '1';

LWL1 <= '1';

FLR <= '0';

Diode_Mode_1 <= '1';

Diode_Mode_2 <= '0';

IGBT_Mode <= '0';--IGBT_Mode is removed

Desat_Done <= '0';

end if;

else

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '1';

if( Z = '0') then

--Vge : -15V using RgD. Transition into

--Diode_Mode from IGBT_Mode

LWL3 <= '1';

LWL2 <= '0';

LWL1 <= '0';

FLR <= '0';

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '1';

IGBT_Mode <= '0';

--IGBT_Mode is removed

Desat_Done <= '0';

else

--Vge : 0V using RgD_OFF and RgN_OFF.

--Transition into Diode_Mode

--from IGBT_Mode

LWL3 <= '1';

LWL2 <= '1';

LWL1 <= '1';

FLR <= '0';

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '1';

IGBT_Mode <= '0';

--IGBT_Mode is removed

Desat_Done <= '0';

end if;

end if;

elsif(Diode_Mode_2 = '1') then

T_interlock <= 0;

T_SC<= 0;

--When Diode Mode 2 is active->---Diode_Mode--Diode_Mode--

--Diode_Mode--Diode_Mode--Diode_Mode---

if( Vce_RC = '1') then

--Vge : +15V using RgNominal(ON)

--Emitter connected to the GND bus

LWL3 <= '0';

LWL2 <= '1';

LWL1 <= '0';

FLR <= '0';

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

IGBT_Mode <= '1';

Do_desat <= '0';

--IGBT_Mode is turned on

Desat_Done <= '0';

elsif((Vce_RC = '0') and (Vce_L = '1')) then

--Vge : +15V using RgN_ON. IGBT_Mode

LWL3 <= '0';

LWL2 <= '1';

LWL1 <= '0';

FLR <= '0';

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

IGBT_Mode <= '1';

--IGBT_Mode is ON

Desat_Done <= '0';

Do_desat <= '0';

else

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '1';

if( Z = '0') then

--Vge : -15V using RgD. Maintain Diode_Mode_2.

LWL3 <= '1';

LWL2 <= '0';

LWL1 <= '0';

FLR <= '0';

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '1';

IGBT_Mode <= '0';

--IGBT_Mode is removed

Desat_Done <= '0';

else

--Vge : 0V using RgD_OFF and RgN_OFF.

--Maintain Diode_Mode_2.

LWL3 <= '1';

LWL2 <= '1';

LWL1 <= '1';

FLR <= '0';

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '1';

IGBT_Mode <= '0';

--IGBT_Mode is removed

Desat_Done <= '0';

end if;

end if;

--When Diode Mode is no longer active-<---

--Diode_Mode---Diode_Mode---Diode_Mode---Diode_Mode---

else

if ( Vce_RC = '0') then

T_interlock <= 0;

if( Z = '0') then

--Vge : -15V using RgD. Transition into

--Diode_Mode from IGBT_Mode

LWL3 <= '1';

LWL2 <= '0';

LWL1 <= '0';

FLR <= '0';

Diode_Mode_1 <= '1';

Diode_Mode_2 <= '0';

IGBT_Mode <= '0';

--IGBT_Mode is removed

Desat_Done <= '0';

else

--Vge : 0V using RgD_OFF and RgN_OFF.

--Transition into.

--Diode_Mode from IGBT_Mode

LWL3 <= '1';

LWL2 <= '1';

LWL1 <= '1';

FLR <= '0';

Diode_Mode_1 <= '1';

Diode_Mode_2 <= '0';

IGBT_Mode <= '0';

--IGBT_Mode is removed

Desat_Done <= '0';

end if;

else

-- Vce_RC = 1 and the Interlock wait period begins

if (Desat_Done = '1') then

if(T_interlock < 2200) then T_interlock <= T_interlock + 1;

--Vge : -15V using RgD

--Emitter connected to +15V Bus

LWL3 <= '1';

LWL2 <= '0';

LWL1 <= '0';

FLR <= '0';

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

IGBT_Mode <= '0';

Desat_Done <= '1';

--Variable ensures continuity in Vge : -15V

-- using RgD when µC = 0

else

--Vge : +15V using RgNominal(ON).

--Emitter connected to the ground bus.

LWL3 <= '0';

LWL2 <= '1';

LWL1 <= '0';

FLR <= '0';

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

IGBT_Mode <= '1';

--IGBT Mode is turned ON

Desat_Done <= '0';

T_interlock <= 0;

Do_desat <= '0';

end if;

else

if(T_interlock < 2200) then T_interlock <= T_interlock + 1;

--Vge : -15V using RgNominal(OFF)

--Emitter connected to +15V Bus

LWL3 <= '0';

LWL2 <= '0';

LWL1 <= '0';

FLR <= '0';

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

IGBT_Mode <= '0';

Desat_Done <= '0';

Do_desat <= '0';

else

--Vge : +15V using RgNominal(ON).

--Emitter connected to the ground bus.

LWL3 <= '0';

LWL2 <= '1';

LWL1 <= '0';

FLR <= '0';

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

IGBT_Mode <= '1';

--IGBT Mode is turned ON

Desat_Done <= '0';

T_interlock <= 0 ;

Do_desat <= '0';

end if;

end if;

end if;

end if;

end if;

------µC Pulse '1' conditions over-------------------------------------------

--end if;

----------µC Pulse 0/1 conditions over----------------------------------------

---------FLR = '0' Conditions over-----------------------------------------------

---------If FLR = '1'---------------------------------------------------------------------

elsif( FLR = '1') then

if( Reset = '1') then

FLR <= '0';

T_SC <= 0 ;

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

IGBT_Mode <= '0';

Desat_Done <= '0';

T_desat := 1 ;

Do_desat <= '0';

else

--Vge : -15V using Rg Nominal(OFF)

LWL3 <= '0';

LWL2 <= '0';

LWL1 <= '0';

FLR <= '1';

------FLR Remains ON in '1' until 'Reset' happens

Diode_Mode_1 <= '0';

Diode_Mode_2 <= '0';

IGBT_Mode <= '0';

Desat_Done <= '0';

T_desat := 1 ;

Do_desat <= '0';

end if;

--FLR = '1' keeps the system in RgNominal OFF state until FLR is reset externally-----

end if;

end if;

end process;

end Behavioral;

[lakshnar]

The lines posted in red are the ones getting unnecessarily executed even when i set the required parameters to zero in other states.

[aher]

hi,

did you check the post implementation simulation of your code?

that may help you understand the bug in your code.

thanks,

Shreyas

----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
Give Kudos (star provided in left) to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

[gszakacs]

There are a number of reasons why a design will fail to match simulation:

1) Insufficiently constrained timing.  At a minimum, there should be a PERIOD constraint on the clock and OFFSET IN BEFORE constraints for each synchronous input to the design.  These constraints need to match the actual conditions presented to the circuit in hardware.

2) Conditions in the hardware do not match those in simulation.

3) Asynchronous inputs to the design are not properly handled.

In your design you have at least 4 inputs that must be synchronous to the clock in order for the design to work properly.  That's because they have direct setup paths to more than one flip-flop in the design.  They are:

Vce_RC, M_in, Reset, and Vcs_L

There may be others, but those were obvious by looking through a timing analysis because they had setup to multiple endpoints.

If any of those signals are not actually synchronous to the clock, they need to be synchronized before applying them to the state machine logic.  If they are synchronous to the clock, they need to meet the setup and hold time specified in your constraints and the constraints must be met.

[lakshnar]

Hi Gabor ! Thank you for the valuble inputs ! Based on your feedback, I have tried to implement the modifications and i have the following observations :

1) Insufficient constrained timing - I have a slack of 90.727 ns ( I reduced my clock  period from 20 ns to 100 ns) and the error persists.

2) Regarding asynchonous inputs and asynchronous signals, I have now kept only 'clk' in the sensitivity list and removed all the other inputs and signals, but with the formation of setup paths to more than one flip-flop in the design, I dont know how that can be elimnated. I would like to know if there is something else i need to do to make to code work 'synchronously' and how I can avoid multiple FF for the same kind of signal.

Thanks again !

Regards,

Narender

[lakshnar]

Hi Shreyas ! I have a strong suspicion that the bug is due to some signals not working in sync with the System as a whole, I would like to know how to make the Inputs and the signals function in sync and how to avoid multiple FFs being Setup for the same kind of Input. I notice in my physical implementation that the same kind of Inputs are giving different outputs.

Could you help me with this ?

Regards,

Narender

[muzaffer]

>> how to make the Inputs and the signals function in sync and how to avoid multiple FFs being Setup for the same kind of Input

this is quite simply. Never use a signal which comes from an external input without pushing it through at least two stages of registers. Say you have an external signal named enable. First register this signal twice and use the output of the second register everywhere you need it.

input enable;

reg enable_r, enable_rr;
always_ff @(posedge clk) begin
enable_r <= enable;
enable_rr <= enable_r;
end

now use only enable_rr where you need enable.

[lakshnar]

Hey Muzzafer ! Thanks a lot ! Will try this approach and checkout the results.

[gszakacs]

---

@muzaffer wrote:
>> how to make the Inputs and the signals function in sync and how to avoid multiple FFs being Setup for the same kind of Input

this is quite simply. Never use a signal which comes from an external input without pushing it through at least two stages of registers. Say you have an external signal named enable. First register this signal twice and use the output of the second register everywhere you need it.

---

To be clear, fixing the problem you've actually seen only requires a single register.  This "single point of entry" into the clock domain is what prevents issues when the input doesn't meet setup on some flops but does on others.  The second register is only required for metastability mitigation, which is something that happens much less frequently.  It would also happen less frequently at lower frequencies due to the increased slack from the first stage (input) register to other registers in the design and may not be required at all for your design.  However adding the second stage is a good idea if you can afford the latency.

[lakshnar]

Hi ! So as per the reccomendations, I have changed the programming style and made 2 levels of internal signals and then values assigned to the output ports.

1 out of 12 times(on an average) , the code mentioned in RED is NOT getting executed when the necessary conditions are provided. Most of the time it works, then suddenly it refuses to do that particular state transition.

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:11:01 11/26/2014
-- Design Name:
-- Module Name: RCDC_WARSTEIN_1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RCDC_WARSTEIN_1 is
Port ( clk : in STD_LOGIC;
M_in : in STD_LOGIC;
Vce_RC: in STD_LOGIC;
Vce_L : in STD_LOGIC;
Z : in STD_LOGIC;
Reset : in STD_LOGIC;

LWL3 : out STD_LOGIC;
LWL2 : out STD_LOGIC;
LWL1 : out STD_LOGIC);
end RCDC_WARSTEIN_1;

architecture Behavioral of RCDC_WARSTEIN_1 is
--constant T_interlock : time := 11000 ns; -- Time for Interlock period
--constant T_desat : time := 10000 ns; -- Time for desaturation period
signal Diode_Mode1 : STD_LOGIC:= '0';
signal Diode_Mode2 : STD_LOGIC:= '0';
signal Diode_Mode1Z : STD_LOGIC:= '0';
signal Diode_Mode2Z : STD_LOGIC:= '0';
signal IGBT_Mode : STD_LOGIC:= '0';
signal Desat_done : STD_LOGIC:= '0';
signal Do_desat : STD_LOGIC:= '0';
signal FLR : STD_LOGIC:= '0';
signal interlock_wait_1 : STD_LOGIC:= '0';
signal interlock_wait_2 : STD_LOGIC:= '0';
signal Normal_OFF : STD_LOGIC:= '0';

signal T_interlock : integer := 0;
signal T_SC : integer := 0;
signal T_desat : integer := 0;

signal EN_desat : STD_LOGIC:= '0';
signal EN_FLR : STD_LOGIC:= '0';
signal EN_Normal_OFF : STD_LOGIC:= '0';
signal EN_Desat_Done : STD_LOGIC:= '0';
signal EN_IGBT_Mode : STD_LOGIC:= '0';
signal EN_Diode_Mode1 : STD_LOGIC:= '0';
signal EN_Diode_Mode2 : STD_LOGIC:= '0';
signal EN_Diode_Mode1Z : STD_LOGIC:= '0';
signal EN_Diode_Mode2Z : STD_LOGIC:= '0';
signal EN_interlock_wait_1 : STD_LOGIC:= '0';
signal EN_interlock_wait_2 : STD_LOGIC:= '0';

--signal T_dst : integer := 2000;
--signal SC : integer := 500;--- Equivalent of 2.5 µS

begin
process(clk,M_in,Vce_RC,Vce_L,Z,Reset,Diode_Mode1,Diode_Mode2,Diode_Mode1Z,Diode_Mode2Z,IGBT_Mode,Desat_done,Do_desat,FLR,interlock_wait_1,interlock_wait_2,Normal_OFF,T_interlock,T_SC,T_desat,EN_desat,EN_FLR,EN_Normal_OFF,EN_Desat_Done,EN_IGBT_Mode,EN_Diode_Mode1,EN_Diode_Mode2,EN_Diode_Mode1Z,EN_Diode_Mode2Z,EN_interlock_wait_1,EN_interlock_wait_2)
--,FLR,M_in,Do_desat,Vce_RC,T_SC,Desat_Done,Diode_Mode_1,Diode_Mode_2,IGBT_Mode,Vce_L,Z,T_interlock,Reset,EN_desat
--VARIABLE T_desat : integer range 0 to 2000000000;
begin

if((clk'event) and (clk = '1')) then

EN_Normal_OFF <= (Normal_OFF) and (not M_in);
EN_desat <= (not FLR) and (Do_desat) and (not M_in);
EN_Desat_Done <= (not FLR) and (Desat_done) and (not M_in);
EN_IGBT_Mode <= (not FLR) and (IGBT_Mode) and (M_in);
EN_Diode_Mode1 <= (not FLR) and (Diode_Mode1) and (M_in) and (not IGBT_Mode) and (not Diode_Mode2);
EN_Diode_Mode2 <= (not FLR) and (Diode_Mode2) and (M_in) and (not IGBT_Mode) and (not Diode_Mode1);
EN_Diode_Mode1Z <= (not FLR) and (Diode_Mode1Z) and (M_in);
EN_Diode_Mode2Z <= (not FLR) and (Diode_Mode2Z) and (M_in);
EN_interlock_wait_1 <= (not FLR) and (interlock_wait_1) and (M_in);
EN_interlock_wait_2 <= (not FLR) and (interlock_wait_2) and (M_in);
EN_FLR <= (FLR) and (not RESET);

if ((M_in = '1') and (Vce_RC = '1') and (Vce_L = '1') and (Desat_done = '1') and (IGBT_Mode = '0') and (Diode_Mode1 = '0') and (Diode_Mode2 = '0') and (Diode_Mode1Z = '0') and (Diode_Mode2Z = '0') and (FLR = '0')) then

--STARTING IN INTERLOCK WAIT MODE WITH MAINTAINING DIODE MODE OFF STATE UNTIL IGBT ON
if(T_interlock < 2200) then T_interlock <= T_interlock + 1;
--LOOP FOR MAINTAINING INTERLOCK WAIT MODE
interlock_wait_1 <= '1';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '0';
T_SC <= 0;
-- FLR <= '0';
Normal_OFF <= '0';
T_desat <= 0;
else
--INTERLOCK WAIT PERIOD COMPLETED. TURN ON IGBT. IGBT MODE IS ON.
T_interlock <= 0;
-- FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '1';
Do_desat <= '0';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;
end if;

elsif ((M_in = '1') and (Vce_RC = '1') and (Vce_L = '1') and (Desat_done = '0') and (IGBT_Mode = '0') and (Diode_Mode1 = '0') and (Diode_Mode2 = '0') and (Diode_Mode1Z = '0') and (Diode_Mode2Z = '0') and (FLR = '0')) then

-- INTERLOCK WAIT WITH NORMAL OFF STATE
if(T_interlock < 2200) then T_interlock <= T_interlock + 1;
--LOOP FOR MAINTAINING THE INTERLOCK WAIT STATE
interlock_wait_1 <= '0';
interlock_wait_2 <= '1';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '0';
T_SC <= 0;
--FLR <= '0';
Normal_OFF <= '0';
T_desat <= 0;

else
-- LOOP COMPLETED, IGBT TURNED ON. IGBT MODE IS ON.
T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '1';
Do_desat <= '0';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;
end if;

elsif ((M_in = '1') and (Vce_RC = '0') and (Vce_L = '1') and (Diode_Mode1 = '0') and (Diode_Mode2 = '0') and (Diode_Mode1Z = '0') and (Diode_Mode2Z = '0') and (IGBT_Mode = '0') and (Z = '0') and (FLR = '0')) then
-- STARTING IN DIODE MODE 1
T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '1';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '1';
T_SC <= 0;
-- Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;

elsif ((M_in = '1') and (Vce_RC = '0') and (Vce_L = '1') and (Diode_Mode1 = '0') and (Diode_Mode2 = '0') and (Diode_Mode1Z = '0') and (Diode_Mode2Z = '0') and (IGBT_Mode = '0') and (Z = '1') and (FLR = '0')) then

-- STARTING IN DIODE MODE 1Z
T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '1';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '1';
T_SC <= 0;
-- Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;

elsif ((M_in = '1') and (Vce_RC = '0') and (Vce_L = '0') and (Diode_Mode1 = '0') and (Diode_Mode2 = '0') and (Diode_Mode1Z = '0') and (Diode_Mode2Z = '0') and (IGBT_Mode = '0') and (Z = '1') and (FLR = '0')) then
--STARTING IN DIODE MODE 2Z
T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '1';
IGBT_Mode <= '0';
Do_desat <= '1';
T_SC <= 0;
-- Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;

elsif ((M_in = '1') and (Vce_RC = '0') and (Vce_L = '0') and (Z = '0') and (FLR = '0')) then
--STARTING IN DIODE MODE 2
T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '1';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '1';
T_SC <= 0;
--Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;

elsif ((M_in = '1') and (Vce_RC = '0') and (Vce_L = '0') and (IGBT_Mode = '1') and (Z = '0') and (FLR = '0')) then
-- TRANSITION FROM IGBT MODE TO DIODE MODE 2
T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '1';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '1';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;

elsif ((M_in = '1') and (Vce_RC = '0') and (Vce_L = '0') and (Diode_Mode1 = '0') and (Diode_Mode2 = '0') and (Diode_Mode1Z = '0') and (Diode_Mode2Z = '0') and (IGBT_Mode = '1') and (Z = '1') and (FLR = '0')) then
-- TRANSITION FROM IGBT MODE TO DIODE MODE 2Z
T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '1';
IGBT_Mode <= '0';
Do_desat <= '1';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;

elsif ((M_in = '1') and (Vce_RC = '0') and (Vce_L = '1') and (Diode_Mode2 = '1') and (FLR = '0')) then
--TRANSITION FROM DIODE MODE 2 TO IGBT MODE
T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '1';
Do_desat <= '0';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;

elsif ((M_in = '1') and (Vce_RC = '0') and (Vce_L = '1') and (Diode_Mode1 = '0') and (Diode_Mode2 = '0') and (Diode_Mode1Z = '0') and (Diode_Mode2Z = '1') and (FLR = '0')) then
--TRANSITION FROM DIODE MODE 2Z TO IGBT MODE
T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '1';
Do_desat <= '0';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;

elsif ((M_in = '1') and (Vce_RC = '1') and (Vce_L = '1') and (Diode_Mode1 = '1') and (Diode_Mode2 = '0') and (Diode_Mode1Z = '0') and (Diode_Mode2Z = '0') and (FLR = '0')) then
--TRANSITION FROM DIODE MODE 1 TO IGBT MODE
T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '1';
Do_desat <= '0';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;

elsif ((M_in = '1') and (Vce_RC = '1') and (Vce_L = '1') and (Diode_Mode1 = '0') and (Diode_Mode2 = '0') and (Diode_Mode1Z = '1') and (Diode_Mode2Z = '0') and (FLR = '0')) then
--TRANSITION FROM DIODE MODE 1Z TO IGBT MODE
T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '1';
Do_desat <= '0';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;

--elsif ((M_in = '1') and (Vce_RC = '0') and (Vce_L = '1') and (Diode_Mode1 = '1') and (Z = '0') and (FLR = '0')) then
--MAINTAIN IN DIODE MODE 1 IF Vce_L = '1'
-- T_interlock <= 0;
--FLR <= '0';
-- interlock_wait_1 <= '0';
-- interlock_wait_2 <= '0';
-- Diode_Mode1 <= '1';
-- Diode_Mode2 <= '0';
-- Diode_Mode1Z <= '0';
-- Diode_Mode2Z <= '0';
-- IGBT_Mode <= '0';
-- Do_desat <= '1';
-- T_SC <= 0;
-- Desat_done <= '0';
-- Normal_OFF <= '0';
-- T_desat <= 0;

elsif ((M_in = '1') and (Vce_RC = '0') and (Vce_L = '1') and (Diode_Mode1 = '0') and (Diode_Mode2 = '0') and (Diode_Mode1Z = '1') and (Diode_Mode2Z = '0') and (Z = '1') and (FLR = '0')) then
--MAINTAIN IN DIODE MODE 1Z IF Vce_L = '1'
T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '1';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '1';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;

elsif ((M_in = '0') and (Diode_Mode1 = '0') and (Diode_Mode2 = '0') and (Diode_Mode1Z = '0') and (Diode_Mode2Z = '0') and (IGBT_Mode = '1') and (FLR = '0')) then
--NORMAL OFF STATE
T_interlock <= 0;
-- FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '0';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '1';
T_desat <= 0;



elsif ((M_in = '0') and (Diode_Mode1 = '1') and (Diode_Mode2 = '0') and (Diode_Mode1Z = '0') and (Diode_Mode2Z = '0') and (IGBT_Mode = '0') and (FLR = '0')) then
--SET FLAG VALUE - DO DESAT = 1 (COMMUTATION DURING DIODE MODE 1)

T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '1';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';

elsif ((M_in = '0') and (Diode_Mode1 = '0') and (Diode_Mode2 = '1') and (Diode_Mode1Z = '0') and (Diode_Mode2Z = '0') and (IGBT_Mode = '0') and (FLR = '0')) then
--SET FLAG VALUE - DO DESAT = 1 (COMMUTATION DURING DIODE MODE 2)

T_interlock <= 0;
-- FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '1';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';

elsif ((M_in = '0') and (Diode_Mode1 = '0') and (Diode_Mode2 = '0') and (Diode_Mode1Z = '1') and (Diode_Mode2Z = '0') and (IGBT_Mode = '0') and (FLR = '0')) then
--SET FLAG VALUE - DO DESAT = 1 (COMMUTATION DURING DIODE MODE 1Z)

T_interlock <= 0;
-- FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '1';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';

elsif ((M_in = '0') and (Diode_Mode1 = '0') and (Diode_Mode2 = '0') and (Diode_Mode1Z = '0') and (Diode_Mode2Z = '1') and (IGBT_Mode = '0') and (FLR = '0')) then
--SET FLAG VALUE - DO DESAT = 1 (COMMUTATION DURING DIODE MODE 2Z)

T_interlock <= 0;
-- FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '1';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';

elsif ((M_in = '0') and (Do_desat = '1') and (Vce_RC = '0') and (FLR = '0')) then
-- START DOING DESAT
if(T_desat < 2000) then T_desat <= T_desat + 1;

T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '1';
EN_desat <= '1';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';

else

T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '0';
EN_desat <= '0';
EN_Desat_done <= '1';
T_SC <= 0;
Desat_done <= '1';
Normal_OFF <= '0';
T_desat <= 0;


end if;

elsif ((M_in = '0') and (Do_desat = '1') and (Vce_RC = '1') and (FLR = '0')) then
-- DONT DO DESAT IF Vce_RC = '1'
T_interlock <= 0;
FLR <= '1';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '0';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;

elsif ((M_in = '0') and (Desat_Done = '1') and (FLR = '0')) then
-- AFTER DESAT COMPLETED, MAINTAIN DESAT DONE FLAG = '1'
T_interlock <= 0;
--FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '0';
T_SC <= 0;
Desat_done <= '1';
Normal_OFF <= '0';
T_desat <= 0;

elsif (FLR = '1') then

T_interlock <= 0;
FLR <= '1';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '0';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;



end if;
---Condition exclusively for checking and handling for short circuit and FLR ---
if ((M_in = '1') and (Vce_RC = '1') and (IGBT_Mode = '1') and (FLR <= '0')) then
--Checking for short circuit during IGBT ON Mode
if(T_SC < 1000) then T_SC <= T_SC + 1;
IGBT_Mode <= '1';
--FLR <= '0';
else
T_interlock <= 0;
FLR <= '1';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '0';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;
end if;

elsif ((FLR = '1') and (RESET = '0')) then
T_interlock <= 0;
FLR <= '1';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '0';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;

elsif ((FLR = '1') and (RESET = '1')) then
T_interlock <= 0;
FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '0';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;

elsif ((FLR = '0') and (RESET = '1')) then
T_interlock <= 0;
FLR <= '0';
interlock_wait_1 <= '0';
interlock_wait_2 <= '0';
Diode_Mode1 <= '0';
Diode_Mode2 <= '0';
Diode_Mode1Z <= '0';
Diode_Mode2Z <= '0';
IGBT_Mode <= '0';
Do_desat <= '0';
T_SC <= 0;
Desat_done <= '0';
Normal_OFF <= '0';
T_desat <= 0;

end if;
--- Values will noe be assigned to the output ports
if ((EN_desat = '1') and (EN_Normal_OFF = '0') and (EN_Desat_Done = '0') and (EN_IGBT_Mode = '0') and (EN_Diode_Mode1 = '0') and (EN_Diode_Mode2 = '0') and (EN_Diode_Mode1Z = '0') and (EN_Diode_Mode2Z = '0') and (EN_interlock_wait_1 = '0') and (EN_interlock_wait_2 = '0') and (EN_FLR = '0')) then
-- Desat process 1,1 output
LWL3 <= '1';
LWL2 <= '1';
LWL1 <= '0';

elsif((EN_desat = '0') and (EN_Normal_OFF = '1') and (EN_Desat_Done = '0') and (EN_IGBT_Mode = '0') and (EN_Diode_Mode1 = '0') and (EN_Diode_Mode2 = '0') and (EN_Diode_Mode1Z = '0') and (EN_Diode_Mode2Z = '0') and (EN_interlock_wait_1 = '0') and (EN_interlock_wait_2 = '0') and (EN_FLR = '0')) then
-- Normal OFF
LWL3 <= '0';
LWL2 <= '0';
LWL1 <= '0';

elsif((EN_desat = '0') and (EN_Normal_OFF = '0') and (EN_Desat_Done = '1') and (EN_IGBT_Mode = '0') and (EN_Diode_Mode1 = '0') and (EN_Diode_Mode2 = '0') and (EN_Diode_Mode1Z = '0') and (EN_Diode_Mode2Z = '0') and (EN_interlock_wait_1 = '0') and (EN_interlock_wait_2 = '0') and (EN_FLR = '0')) then
-- Stay at Desat done mode
LWL3 <= '1';
LWL2 <= '0';
LWL1 <= '0';

elsif((EN_desat = '0') and (EN_Normal_OFF = '0') and (EN_Desat_Done = '0') and (EN_IGBT_Mode = '1') and (EN_Diode_Mode1 = '0') and (EN_Diode_Mode2 = '0') and (EN_Diode_Mode1Z = '0') and (EN_Diode_Mode2Z = '0') and (EN_interlock_wait_1 = '0') and (EN_interlock_wait_2 = '0') and (EN_FLR = '0')) then
-- Stay at IGBT mode
LWL3 <= '0';
LWL2 <= '1';
LWL1 <= '0';

elsif((EN_desat = '0') and (EN_Normal_OFF = '0') and (EN_Desat_Done = '0') and (EN_IGBT_Mode = '0') and (EN_Diode_Mode1 = '1') and (EN_Diode_Mode2 = '0') and (EN_Diode_Mode1Z = '0') and (EN_Diode_Mode2Z = '0') and (EN_interlock_wait_1 = '0') and (EN_interlock_wait_2 = '0') and (EN_FLR = '0')) then
-- Stay at Diode mode1
LWL3 <= '1';
LWL2 <= '0';
LWL1 <= '0';

elsif((EN_desat = '0') and (EN_Normal_OFF = '0') and (EN_Desat_Done = '0') and (EN_IGBT_Mode = '0') and (EN_Diode_Mode1 = '0') and (EN_Diode_Mode2 = '1') and (EN_Diode_Mode1Z = '0') and (EN_Diode_Mode2Z = '0') and (EN_interlock_wait_1 = '0') and (EN_interlock_wait_2 = '0') and (EN_FLR = '0')) then
-- Stay at Diode mode2
LWL3 <= '1';
LWL2 <= '0';
LWL1 <= '0';

elsif((EN_desat = '0') and (EN_Normal_OFF = '0') and (EN_Desat_Done = '0') and (EN_IGBT_Mode = '0') and (EN_Diode_Mode1 = '0') and (EN_Diode_Mode2 = '0') and (EN_Diode_Mode1Z = '1') and (EN_Diode_Mode2Z = '0') and (EN_interlock_wait_1 = '0') and (EN_interlock_wait_2 = '0') and (EN_FLR = '0')) then
-- Stay at Diode mode1Z
LWL3 <= '1';
LWL2 <= '1';
LWL1 <= '1';

elsif((EN_desat = '0') and (EN_Normal_OFF = '0') and (EN_Desat_Done = '0') and (EN_IGBT_Mode = '0') and (EN_Diode_Mode1 = '0') and (EN_Diode_Mode2 = '0') and (EN_Diode_Mode1Z = '0') and (EN_Diode_Mode2Z = '1') and (EN_interlock_wait_1 = '0') and (EN_interlock_wait_2 = '0') and (EN_FLR = '0')) then
-- Stay at Diode mode2Z
LWL3 <= '1';
LWL2 <= '1';
LWL1 <= '1'; --

elsif((EN_desat = '0') and (EN_Normal_OFF = '0') and (EN_Desat_Done = '0') and (EN_IGBT_Mode = '0') and (EN_Diode_Mode1 = '0') and (EN_Diode_Mode2 = '0') and (EN_Diode_Mode1Z = '0') and (EN_Diode_Mode2Z = '0') and (EN_interlock_wait_1 = '1') and (EN_interlock_wait_2 = '0') and (EN_FLR = '0')) then
-- Stay at interlock wait 1 mode
LWL3 <= '1';
LWL2 <= '0';
LWL1 <= '0';

elsif((EN_desat = '0') and (EN_Normal_OFF = '0') and (EN_Desat_Done = '0') and (EN_IGBT_Mode = '0') and (EN_Diode_Mode1 = '0') and (EN_Diode_Mode2 = '0') and (EN_Diode_Mode1Z = '0') and (EN_Diode_Mode2Z = '0') and (EN_interlock_wait_1 = '0') and (EN_interlock_wait_2 = '1') and (EN_FLR = '0')) then
-- Stay at interlock wait 2
LWL3 <= '0';
LWL2 <= '0';
LWL1 <= '0';

elsif((EN_desat = '0') and (EN_Normal_OFF = '0') and (EN_Desat_Done = '0') and (EN_IGBT_Mode = '0') and (EN_Diode_Mode1 = '0') and (EN_Diode_Mode2 = '0') and (EN_Diode_Mode1Z = '0') and (EN_Diode_Mode2Z = '0') and (EN_interlock_wait_1 = '0') and (EN_interlock_wait_2 = '0') and (EN_FLR = '1')) then
--FAILURE MODE
LWL3 <= '0';
LWL2 <= '0';
LWL1 <= '0';

elsif((EN_desat = '0') and (EN_Normal_OFF = '0') and (EN_Desat_Done = '0') and (EN_IGBT_Mode = '0') and (EN_Diode_Mode1 = '0') and (EN_Diode_Mode2 = '0') and (EN_Diode_Mode1Z = '0') and (EN_Diode_Mode2Z = '0') and (EN_interlock_wait_1 = '0') and (EN_interlock_wait_2 = '0') and (EN_FLR = '0') and (desat_done = '1')) then
--If all = 0 but Desat_done = '1'
LWL3 <= '1';
LWL2 <= '0';
LWL1 <= '0';

else

LWL3 <= '0';
LWL2 <= '0';
LWL1 <= '0';

end if;
end if;

end process;
end Behavioral;

Kindly let me know if there may be something else entirely wrong somewhere...

Timing constraints  detail for Diode_Mode2 state, I dont know why it maps this to the EN_Diode_Mode1 signal ??

--------------------------------------------------------------------------------

 Paths for end point EN_Diode_Mode1 (SLICEL.SR), 1 path 

 -------------------------------------------------------------------------------- 

 Slack (hold path):      0.863ns (requirement - (clock path skew + uncertainty - data path)) 

   Source:               Diode_Mode2 (FF) 

   Destination:          EN_Diode_Mode1 (FF) 

   Requirement:          0.000ns 

   Data Path Delay:      0.863ns (Levels of Logic = 0) 

   Clock Path Skew:      0.000ns 

   Source Clock:         clk_BUFGP rising at 100.000ns 

   Destination Clock:    clk_BUFGP rising at 100.000ns 

   Clock Uncertainty:    0.000ns 

   Minimum Data Path: Diode_Mode2 to EN_Diode_Mode1 

     Location             Delay type         Delay(ns)  Physical Resource 

                                                        Logical Resource(s) 

     -------------------------------------------------  ------------------- 

     SLICEL.XQ            Tcko                  0.473   Diode_Mode2 

                                                        Diode_Mode2 

     SLICEL.SR            net (fanout=16)    e  0.100   Diode_Mode2 

     SLICEL.CLK           Tcksr       (-Th)    -0.290   EN_Diode_Mode1 

                                                        EN_Diode_Mode1 

     -------------------------------------------------  --------------------------- 

     Total                                      0.863ns (0.763ns logic, 0.100ns route) 

                                                        (88.4% logic, 11.6% route) 

--------OVERALL----

All constraints were met.

 Data Sheet report: 

 ----------------- 

 All values displayed in nanoseconds (ns) 

 Clock to Setup on destination clock clk 

 ---------------+---------+---------+---------+---------+ 

                | Src:Rise| Src:Fall| Src:Rise| Src:Fall| 

 Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| 

 ---------------+---------+---------+---------+---------+ 

 clk            |    6.892|         |         |         | 

 ---------------+---------+---------+---------+---------+ 

  Timing summary: 

 --------------- 

 Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0) 

 Constraints cover 13416 paths, 0 nets, and 1284 connections 

  Design statistics: 

    Minimum period:   6.892ns{1}   (Maximum frequency: 145.096MHz) 

 ------------------------------------Footnotes----------------------------------- 

 1)  The minimum period statistic assumes all single cycle delays. 

 Analysis completed Tue Jan 13 22:39:15 2015  

 -------------------------------------------------------------------------------- 

  Trace Settings: 

 ------------------------- 

 Trace Settings  

 Peak Memory Usage: 189 MB 

[muzaffer]

Make sure that the following inputs are synchronous to your clock domain: M_in, Vce_RC, Vce_L , Z. If they are not you need to synchronize them. Register them twice and put async_reg property on those registers.

[lakshnar]

HI Muzzafer !

Thanks , I get you point, I will now implement the following for all my inputs external signals :

en1_M_in <= M_in ;

en2_M_in <= en1_M_in ;

I wil then use only en2_M_in for all further logical interaction with my internal signals.

I will put this inside the if(clk'event and clk = '1') loop, so that the signal en2_M_in is synced to clk.

But could you explain what you mean by "and put async_reg property on those registers."  Nothing is async anymore, right?

[gszakacs]

I wasn't aware that async_reg was available in ISE.  I thought it was just for Vivado.  It makes sure that certain types of optimization are not allowed in order to minimize the possibility of metastability.  In ISE the closest equivalent is to set a FROM : TO constraint on the path from the first to the second flip-flop with a time that is significantly shorter than the clock period.  Also if you place the first flip-flop in the IOB or add an asynchronous reset to both flops you will prevent the use of SRL (LUT-based shift register) for these signals.  The idea is that you want extra slack in the path between the two synchronizer flip-flops.  In any case, below about 50 MHz on Spartan 3A this is all serious overkill because you're likely to already have lots of slack between the two flops when there is no intervening LUT regardless of the flip-flop placement and routing.

[muzaffer]

async_reg has been available for a very long time: http://www.xilinx.com/itp/xilinx10/books/docs/cgd/cgd.pdf

I am not sure how much physical design optimization it caused in xst/par but it they did the right thing for simulation.

[muzaffer]

async_reg signifies that the input to a register is asynchronous to the clock of the said flop. It's a good idea for the first register in the chain.