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Registered: ‎08-23-2011

xilinx ise 14.1 and synplify pro ... flow and questions regarding clock constraints ...



i have some questions reg. xilinx 14.1 and synplify pro. 


>I am envoking synplify pro from within xilinx for synthesizing my design. then design is implemented (map/p&r) using xilinx flow.

>the i/p clock to my design is 100M, there is a xilinx coregen PLL that generates 20M and 40M clocks (from the 100M clock) for the rest of my design.


please excuse if my questions are silly :) but here goes -


1)in xilinx ise 14.1, i have a .ucf file to constraint the i/p clock to 100M. do i also need to constraint the 20M and 40M clocks which are generated by the Xilinx PLL?


2)since the ucf file specified is in xilinx, does this file get picked up when synplify is synthesizing the design?


3)if the ucf file is not picked by synplify, then do i need to make a seperate file for synplify (.sdc file) and specify the constraints for the 100M clock in it? and do i need to constaint the 20M and 40M clocks too?


4)if i am running synplify from within xilinx for synthesis, then can i be sure that synplify does pick up the xilinx coregen cores?


5)i did run synplify on my design from within xilinx and the synthesis passed. but when i open the .prj file in standalone mode, i dont see a seperate sub-folder for the xilinx cores but I do see that the .v files for those cores are in the synplify heirarchy. so is that enough to point synplify to the xilinx coregen cores or do i need to add something else in standalone mode?


6)after running synplify, i see a couple of files generated - top.sdc and AutoConstrant_top.sdc - these files give me the feeling that synplify may also need some constraints - so which file should i modify to add my constraints - top.sdc or AutoConstraint_top.sdc?


7)in the above .sdc file, should i constraint only the i/p 100M clock or also the 20, 40M clocks?


8)do i need to change the implementation options in synplify from "auto constraint" to a specific frequency? in general, should i constraint my design for the max freq and assume that the tool (xilinx or synplify) will automatically constraint the derived clocks?


loads of questions but please do help ... 


thanks in advance ...





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