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Contributor
Contributor
164 Views
Registered: ‎10-29-2018

xpm_memory_dprom not found??

I have a design in which I'm trying to instantiate a dual port rom using the library macro xpm_memory_dprom. I used the Verilog instantiation method outlined in UG974. The code is attached.

When I put the module within my block design and click on Generate Output Products, the multiple block runs kicks off. I get the following error when it's time for the ROM to compile. Any ideas?

 


*** Running vivado
with args -log dataflow_hologram_rom_banks_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dataflow_hologram_rom_banks_0.tcl


****** Vivado v2019.1 (64-bit)
**** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
**** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source dataflow_hologram_rom_banks_0.tcl -notrace
Command: synth_design -top dataflow_hologram_rom_banks_0 -part xcvu095-ffva2104-2-e -mode out_of_context
Starting synth_design
WARNING: [IP_Flow 19-3571] IP 'dataflow_hologram_rom_banks_0' is restricted:
* Module reference is stale and needs refreshing.
Attempting to get a license for feature 'Synthesis' and/or device 'xcvu095'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu095'
INFO: [Device 21-403] Loading part xcvu095-ffva2104-2-e
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 3328
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1164.223 ; gain = 168.594
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'dataflow_hologram_rom_banks_0' [c:/Users/Sandip/Desktop/PLnH/Code/hologram_oddr/bd/dataflow/ip/dataflow_hologram_rom_banks_0/synth/dataflow_hologram_rom_banks_0.v:58]
INFO: [Synth 8-6157] synthesizing module 'hologram_rom_banks' [C:/Users/Sandip/Desktop/PLnH/Code/hologram_oddr/rtl/bitplane_data_32.v:3]
ERROR: [Synth 8-439] module 'xpm_memory_dprom' not found [C:/Users/Sandip/Desktop/PLnH/Code/hologram_oddr/rtl/bitplane_data_32.v:122]
Parameter ADDR_WIDTH_A bound to: 32'sb00000000000000000000000000010001
Parameter ADDR_WIDTH_B bound to: 32'sb00000000000000000000000000010001
Parameter AUTO_SLEEP_TIME bound to: 32'sb00000000000000000000000000000000
Parameter CASCADE_HEIGHT bound to: 32'sb00000000000000000000000000000000
Parameter CLOCKING_MODE bound to: common_clock - type: string
Parameter ECC_MODE bound to: no_ecc - type: string
Parameter MEMORY_INIT_FILE bound to: init.mem - type: string
Parameter MEMORY_INIT_PARAM bound to: (null) - type: string
Parameter MEMORY_OPTIMIZATION bound to: true - type: string
Parameter MEMORY_PRIMITIVE bound to: block - type: string
Parameter MEMORY_SIZE bound to: 32'sb00000000001010001110100000000000
Parameter MESSAGE_CONTROL bound to: 32'sb00000000000000000000000000000001
Parameter READ_DATA_WIDTH_A bound to: 32'sb00000000000000000000000000100000
Parameter READ_DATA_WIDTH_B bound to: 32'sb00000000000000000000000000100000
Parameter READ_LATENCY_A bound to: 32'sb00000000000000000000000000000001
Parameter READ_LATENCY_B bound to: 32'sb00000000000000000000000000000001
Parameter READ_RESET_VALUE_A bound to: 0 - type: string
Parameter READ_RESET_VALUE_B bound to: 0 - type: string
Parameter RST_MODE_A bound to: SYNC - type: string
Parameter RST_MODE_B bound to: SYNC - type: string
Parameter SIM_ASSERT_CHK bound to: 32'sb00000000000000000000000000000001
Parameter USE_MEM_INIT bound to: 32'sb00000000000000000000000000000001
Parameter WAKEUP_TIME bound to: disable_sleep - type: string
ERROR: [Synth 8-6156] failed synthesizing module 'hologram_rom_banks' [C:/Users/Sandip/Desktop/PLnH/Code/hologram_oddr/rtl/bitplane_data_32.v:3]
ERROR: [Synth 8-6156] failed synthesizing module 'dataflow_hologram_rom_banks_0' [c:/Users/Sandip/Desktop/PLnH/Code/hologram_oddr/bd/dataflow/ip/dataflow_hologram_rom_banks_0/synth/dataflow_hologram_rom_banks_0.v:58]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1227.672 ; gain = 232.043
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
5 Infos, 1 Warnings, 0 Critical Warnings and 4 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Fri Sep 6 14:01:48 2019...

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2 Replies
Xilinx Employee
Xilinx Employee
104 Views
Registered: ‎04-19-2010

Re: xpm_memory_dprom not found??

Can you try an experiment?  In your dataflow_hologram_rom_banks_0.tcl before running synth_design but after any read_verilog/read_vhdl commands, can you try the following command :

auto_detect_xpm

This will go through your RTL and detect if you are using any XPMs and then set up the corect libraries for you.

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Contributor
Contributor
86 Views
Registered: ‎10-29-2018

Re: xpm_memory_dprom not found??

Thanks for your response. I tried your experiment. A couple of data points:

1) Before running the experiement, I looked at the dataflow_hologram_rom_banks_0.tcl from two separate projects that use the same rom block. In one project it works without me running your experiment, in the second it doesn't  In the project where it works, the tcl file contains the line

set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]

In the project where I'm having the issue that started this thread, I see

set_property XPM_LIBRARIES XPM_CDC [current_project]

No clue why there would be this diffference

2) When I added your recommended command in the above tcl file and sourced that file in the tcl concole, it looks like it worked and ran.However:

3) I don't want to have to run the tcl file for one submodule in my design manually and independently of the rest of the design, and

4) After the synthesis finished, the overall project seems to think the synthesis is out of date. It isn't updating the status for the rom block and is preventing me from moving forward and running Implementation.

Is there a way to force the status to include the synthesis run results from 2)?

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