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morizzo
Visitor
Visitor
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Registered: ‎04-13-2021

xpm_memory_tdpram fell back from UltraRAM to BlockRAM when synthesized and instantiated

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I expect that xpm_memory_tdpram instantiates 16 cascaded UltraRAMs with asynmetric port widths using the following code. But after synthesis Resource utilization report showed that it instantiated with 64 BlockRAMs instead of UltraRAMs.

Is there any limitation to have Vivado synthesis to infer URAM rather than BRAM?

Note that MEMORY_PRIMITIVE attribute is explicitly set to "ultra".

 

constant ADDR_WIDTH : integer := 16; -- 0~65535
constant DATA_WIDTH : integer := 32; -- float(single precision)

constant DEPTH : integer := 2**ADDR_WIDTH;
constant MEMORY_SIZE : integer := DATA_WIDTH * DEPTH;

constant DATA_WIDTH_B : integer := DATA_WIDTH;
constant ADDR_WIDTH_B : integer := ADDR_WIDTH;

constant DATA_WIDTH_A : integer := 8;
constant ADDR_WIDTH_A : integer := ADDR_WIDTH + 2;

~~

u : xpm_memory_tdpram
generic map (
  ADDR_WIDTH_A => ADDR_WIDTH_A,
  ADDR_WIDTH_B => ADDR_WIDTH_B,
  AUTO_SLEEP_TIME => 0,
  BYTE_WRITE_WIDTH_A => DATA_WIDTH_A,
  BYTE_WRITE_WIDTH_B => DATA_WIDTH_B,
  --CASCADE_HEIGHT => 0,
  CLOCKING_MODE => "common_clock",
  ECC_MODE => "no_ecc",
  MEMORY_INIT_FILE => MEMORY_INIT_FILE,
  MEMORY_INIT_PARAM => "0",
  MEMORY_OPTIMIZATION => "true",
  MEMORY_PRIMITIVE => "ultra",
  MEMORY_SIZE => MEMORY_SIZE,
  MESSAGE_CONTROL => 0,
  READ_DATA_WIDTH_A => DATA_WIDTH_A,
  READ_DATA_WIDTH_B => DATA_WIDTH_B,
  READ_LATENCY_A => 2,
  READ_LATENCY_B => 2,
  READ_RESET_VALUE_A => "0",
  READ_RESET_VALUE_B => "0",
  RST_MODE_A => "SYNC",
  RST_MODE_B => "SYNC",
  --SIM_ASSERT_CHK => 0,
  USE_EMBEDDED_CONSTRAINT => 0,
  USE_MEM_INIT => 1,
  WAKEUP_TIME => "disable_sleep",
  WRITE_DATA_WIDTH_A => DATA_WIDTH_A,
  WRITE_DATA_WIDTH_B => DATA_WIDTH_B,
  WRITE_MODE_A => "no_change",
  WRITE_MODE_B => "no_change"
)
port map (
  rsta => rst,
  clka => clk,
  ena => have_cmd,
  wea(0) => sync_wea,
  addra => sync_addra,
  dina => sync_dina,
  douta => sync_douta,
  sbiterra => open,
  dbiterra => open,
  injectdbiterra => '0',
  injectsbiterra => '0',
  regcea => '1',

  rstb => rst,
  clkb => clk,
  enb => enb,
  web(0) => '0', -- writeしない
  addrb => addrb,
  dinb => (others => '0'),
  doutb => doutb_pre,
  sbiterrb => open,
  dbiterrb => open,
  injectdbiterrb => '0',
  injectsbiterrb => '0',
  regceb => '1',

  sleep => '0'
);

 

Should both of port A/B widths be symmetric or fixed to 64/72?

Simulation works fine and synthesis also looks fine but includes some timing warnings with xpm macro.

 

Vivado 2019.3

Target device is Kintex Ultra scale+ device

 

Thanks

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1 Solution

Accepted Solutions
viviany
Xilinx Employee
Xilinx Employee
360 Views
Registered: ‎05-14-2008

There is no support for configurable port widths of a single 4K x 72 UltraRAM.

That is to say, based on the same URAM cascading structure you can not simply have different width for read and write as port width is not configurable for single URAM cell.

Currently this is not supported with XPM.

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5 Replies
viviany
Xilinx Employee
Xilinx Employee
457 Views
Registered: ‎05-14-2008

Asymmetric port width is not supported when MEMORY_PRIMITIVE is set to URAM.

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
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-------------------------------------------------------------------------------------------------
morizzo
Visitor
Visitor
436 Views
Registered: ‎04-13-2021

Hi viviany,

 

Thank you for clarifying the limitation.

Did I overlook description about such limitation in UG974 or other documents?

Or is there any warnings/suggestion in synthesis log?

 

Thanks,

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richardhead
Scholar
Scholar
404 Views
Registered: ‎08-01-2012

URAM behaviour and setup can be read in UG573 https://www.xilinx.com/support/documentation/user_guides/ug573-ultrascale-memory-resources.pdf

URAM has a fixed data port width of 72

viviany
Xilinx Employee
Xilinx Employee
361 Views
Registered: ‎05-14-2008

There is no support for configurable port widths of a single 4K x 72 UltraRAM.

That is to say, based on the same URAM cascading structure you can not simply have different width for read and write as port width is not configurable for single URAM cell.

Currently this is not supported with XPM.

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

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morizzo
Visitor
Visitor
332 Views
Registered: ‎04-13-2021

Hi viviany,

 

Thank you very much for your information as Xilinx employee.

I've learned URAM has Byte-Write-Enable pins that let us write data in byte so I expected that XPM macro automatically integrated internal logic to support asymmetric port widths even for URAM.

Now I think I can move forward to write my own logic to do that using URAM288 primitive instead.

Thanks,