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Terminology for IP Flow

by Xilinx Employee on ‎10-26-2016 04:54 PM (761 Views)

The Xilinx IP based flow uses terminology that is different from the terms used by typical RTL based designers.

As a result, we need to define certain terminology which might be unique to our IP Flow.

This blog article will attempt to demystify the terminology for flows related to IP.


Managing MicroBlaze Subsystem or DDR Controllers in Update Region of a Tandem with Field Updates Design

by Xilinx Employee ‎05-19-2016 05:39 PM - edited ‎05-19-2016 06:14 PM (2,093 Views)

Adding soft IP Cores such as MicroBlaze Subsystems or DDR Controllers as part of the Update Region of a Tandem with Field Updates Design.


Output Delay

by Xilinx Employee on ‎01-28-2016 01:55 PM (2,062 Views)

In this article, we will discuss the concept behind output_delay.


High Impedance and Out of Context (OOC) Synthesis

by Xilinx Employee on ‎11-05-2015 04:04 PM (2,363 Views)

Vivado allows for a portion of the design to be synthesized Out-Of-Context (OOC).

The basic idea with an OOC flow is that a part of the design is synthesized by itself.


Constraining Asynchronous Clocks

by Xilinx Employee on ‎09-30-2015 02:40 PM (4,430 Views)

For asynchronous clocks, there are four ways to write the constraints.


Time Borrowing in Latches

by Xilinx Employee on ‎08-28-2015 09:28 AM (4,996 Views)

Static Timing Analysis applies a concept called Time Borrowing for latch based designs.

This blog post explains time-borrowing, and is relevant to cases where your design has latches, and your timing report has time-borrowing.


Ensuring Skew Control on Data Lines

by Xilinx Employee on ‎08-02-2015 10:44 PM (3,108 Views)

Sometimes, we might want a few signals to appear at more or less the same time time (i.e. the skew between these signals should not be beyond a certain limit).

A typical situation could be multiple bits of a bus, which should be arriving (almost) together.


Preventing Pulse Filtering in Simulation

by Xilinx Employee on ‎06-04-2015 10:44 AM (2,707 Views)

In general, if your design is passing simulation at a lower frequency but failing at a higher frequency, your first question should be whether the design is “timing clean” at the specified higher frequency.


Why do I get reverse pessimism reduction during CPR?

by Xilinx Employee ‎04-15-2015 11:08 PM - edited ‎04-15-2015 11:20 PM (1,787 Views)

On Chip Variation leads to extreme pessimism in timing analysis.

A portion of this pessimism is recovered through what is called Clock Pessimism Reduction (CPR).

However, we often get queries from users saying that in their designs, instead of recovering a portion of the pessimism, the CPR section is actually doing the opposite, causing them to lose on timing (rather than gaining).


About the blogger...

by Xilinx Employee on ‎03-20-2015 03:53 PM (1,777 Views)

This blog will focus on technical articles explaining how to achieve something specific with XLNX tools and solutions, or explaining some specific aspect of the tool behavior.


About the Author
  • Avinash Thakare joined Xilinx in 2009. He graduated in Electronics Engineering in year 2000; and since then have been working in FPGA and EDA domain. Most of his work experience in FPGA based design and development
  • Sanjay joined Xilinx in 2011. He graduated in Electronics Engg from Indian Institute of Technology (IIT), Kharagpur in 1993; and since then have been working in VLSI and EDA domain. Most of his work experience has been in India, with a brief stint of a few years in Silicon Valley, CA.