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nadaumtimuj
Adventurer
Adventurer
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Registered: ‎01-29-2021

A lot of clocks required--Ring oscillator or something else?

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Hi my FPGA design needs at least 1000 local clocks that are different in frequency and phase. I am thinking about ring oscillators. Is there any better idea?

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

your clocks will NOT be random, but will synchronise,

Also 

https://core.ac.uk/download/pdf/36131749.pdf

 

Also , note you are fighting the tools to make ring oscilators,

    the tools are designed to remove duplicate / redundant gates, 

       so cascaded buffers are removed. 

The tools are also trying to route effectively, which is not compatible with your desire for control of placement,

All the tool problems can be overcome,

but the fact the oscillators will tend to lock and not be statistically independent is a real problem,

 

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surajc
Xilinx Employee
Xilinx Employee
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Registered: ‎01-30-2019

Hi @nadaumtimuj 

why do you require these many different clocks in your design? what are you trying to design? 

Tagging some other users who can help 
@avrumw markg@prosensing.com @dpaul24 
@yashp  @viviany 

dpaul24
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Registered: ‎08-07-2014

@nadaumtimuj ,

I saw this post, but initially I refrained from commenting. But now that I am tagged......

Obviously this post requires more clarity and details. Depending on the requirements and functionality, a fitting architecture has be agreed upon.

my FPGA design needs at least 1000 local clocks that are different in frequency and phase.

If these 1000 clocks are just required with an FPGA region (i.e. signals are not crossing the horizontal and vertical regions) then the mechanism to propagate those clocks will be different than when clocks are traversing all regions withing the entire FPGA. In the latter scenario, for any Xilinx FPGA, there are not enough BUF*s for driving the clock lines. It is a very complicated scenario to work with 1000s clocks, and the question to be asked first is, whether 1000 clocks are really needed.

So we need a detailed explanation as to what the OP is trying to achieve.

------------FPGA enthusiast------------
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nadaumtimuj
Adventurer
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Registered: ‎01-29-2021

@dpaul24 @surajc  Thanks. This is part of a research project and I cannot explain the whole idea for obvious reasons. Imagine it like this: you have thousand 1000 people in a room and everyone has their private clock. Everyone will pass a single DATA to everyone else whenever their own clock ticks. Everyone will receive 999 data from the other people and sum it all to have a new DATA. The clocks need to be fairly different in frequency and phase so that there can be a small delay between sending and receiving the data. In fpga, people will be registers. data will be their values, and clocks will be ring oscillator or something else. Jitter is very welcome because it helps the process further.

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Registered: ‎01-22-2015

@nadaumtimuj 

The clocks need to be fairly different in frequency and phase...  Jitter is very welcome because it helps the process further.

It sounds like you don't care about the quality of the clocks.  In fact, maybe bad clocks are good for your research.  You can get 1000 bad clocks by creating them and routing them in the FPGA fabric.  That is, don't use clocking components (eg. MMCM, PLL) or clock buffers (eg. BUFG) for all the clocks. 

Please read Avrum's recent post about logic-generated/fabric-generated clocks.

I'm don't know if Vivado timing analysis cannot handle 1000 clocks.  Perhaps you will discover the answer to this question during your research and tell us.

Cheers,
Mark

yashp
Moderator
Moderator
578 Views
Registered: ‎01-16-2013

I agree with markg@prosensing.com  Fabric clocks are only the options if you really need 1000 clocks in your design. Those will have quality issues like jitter and I guess you needed that for experiment.

This is very new use case, I have never come across this usage/experiment before hence we do not have any concrete answer on how tool will behave etc. You need to experiment it and find out your own results.

the one important point here is 1000 clocks will interact with each other hence lot of CDCs needed if you want to capture it properly and at the same time constraints management will be little difficult to baseline it in order to get timing closed results.

Thanks,
Yash

 

drjohnsmith
Teacher
Teacher
554 Views
Registered: ‎07-09-2009

I'm guessing your doing some sort of random number generator or noise generator

   As such, do some research on ring oscillators synchronising to each other. 

something like this but in the silicon

https://www.livescience.com/51644-why-pendulum-clocks-sync-up.html

 

 

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nadaumtimuj
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Registered: ‎01-29-2021

markg@prosensing.com Exactly, I need bad clocks. That's why I implemented ring oscillators. Bur ring oscillators are so expensive, I may even need 1000 gates to create the phase shift. I read the post you mentioned but I am not sure how to implement a fabric clock. Do you have any example on this? Thanks.

@yashp Those will have quality issues like jitter and I guess you needed that for experiment. - yes, that's correct.

@drjohnsmith That's also correct. I want some noise in my clocks so that they can never resemble each other in the long run!

Thanks!

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

your clocks will NOT be random, but will synchronise,

Also 

https://core.ac.uk/download/pdf/36131749.pdf

 

Also , note you are fighting the tools to make ring oscilators,

    the tools are designed to remove duplicate / redundant gates, 

       so cascaded buffers are removed. 

The tools are also trying to route effectively, which is not compatible with your desire for control of placement,

All the tool problems can be overcome,

but the fact the oscillators will tend to lock and not be statistically independent is a real problem,

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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495 Views
Registered: ‎01-22-2015

@nadaumtimuj 

I read the post you mentioned but I am not sure how to implement a fabric clock. Do you have any example on this?

As shown in the below Fig 3-5 from UG903(v2020.2), a clock from the clock tree (ie. the input to the C-pin of REGA) can be divided-down to create a fabric clock (ie. the output of the Q-pin of REGA).  

fabric_clock.jpg

To be precise, the signal on the Q-pin of REGA is called a toggle.  However, as shown in UG903, we can specify that this toggle is a clock named clkdiv2 using the following constraint.

 

create_generated_clock -name clkdiv2 -source [get_pins REGA/C] -divide_by 2 [get_pins REGA/Q]

 

As Fig 3-5 shows, clkdiv2 has not been routed through a clock buffer (eg. BUFG) to reach the C-pin of REGB.  This means that clkdiv2 has been routed through the FPGA fabric - and is why we call it a logic-generated fabric-routed clock.  As Avrum explains in the post I mentioned, a clock routed through the fabric can pickup noise and phase shifts that degrade the quality of the clock.

Here's some VHDL that shows how to create clkdiv2 in Fig 3-5 from clkin.

    P1: process(clkin)
    begin
        if rising_edge(clkin) then
            REGA <= NOT(REGA);
        end if;
    end process P1;


Fig 3-5 shows a divide-down of 2 but you can divide-down a clock by any integer using HDL code.

Finally, as yashp mentions, transferring data from circuits clocked by one clock to circuits clocked by another clock is called a clock-domain-crossing (CDC) of the data.  Normally, special clock-domain-crossing-circuits (CDCCs) are needed to make this kind of data transfer happen successfully.  Without a CDCC, the data will sometimes successfully make the crossing - and sometimes not.  However, perhaps the uncertainty of these CDC will improve your research?

Cheers,
Mark

 

 

drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

The thing to note re a fabric clock, is that all derived clocks will be synchronous to the master clock, 

     no randomness,

great for normal FPGAs but if you are after a random number generator, not what you want.

 

 

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