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Observer mogarfield
Observer
2,841 Views
Registered: ‎08-08-2017

A partial reconfigurable project with negative WNS and TNS

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Hello, everyone.

 

We established a partial reconfigurable project. 

 

It can be implemented although it has negative WNS and TNS. But it seems work failed on board. When the project is not converted to partial reconfiguration, it works well and with normal and positive WNS and TNS.

Additional information:  When the project is not converted to partial reconfiguration, it works well and with normal and positive WNS and TNS.

 

My question is here. Is the timing violation or the reconfigurable conversation causes the failed run on board?  I have changed the location for Pblock but it has little effect.

 

If it is caused by the timing violation instead of the reconfigurable conversation. How can I find the key path that should be improved?  

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Voyager
Voyager
5,037 Views
Registered: ‎06-24-2013

Re: A partial reconfigurable project with negative WNS and TNS

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Hey @mogarfield,

 

First I'd check what pathes cause the problem with something like:

report_timing -no_header -path_type summary -max_paths 1000 -slack_lesser_than 0 -setup
report_timing -no_header -path_type summary -max_paths 1000 -slack_lesser_than 0 -hold

Then you inspect the problematic pathes and see if the problem is caused by too deep logic or too much routing delay. The GUI helps there as you can view the Schematic for each path and also the actual routing inside the FPGA.

 

Based on the information gathered, you can usually rearrange or redesign to make it fit.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!

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Voyager
Voyager
2,835 Views
Registered: ‎06-24-2013

Re: A partial reconfigurable project with negative WNS and TNS

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Hey @mogarfield

 

Is the timing violation or the reconfigurable conversation causes the failed run on board?

Most likely the timing violation is the reason your bitstream doesn't work as expected.

 

That said, the partial reconfiguration is most likely the reason for the timing violation in the first place :)

 

Partial reconfiguration requires the interfaces between static and dynamic blocks to be locked in place which usually adds some delay to those pathes. If your timing is already a tight fit without that, it is likely to break und those additional constraints.

 

Hope this clarifies,

Herbert

-------------- Yes, I do this for fun!
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Observer mogarfield
Observer
2,828 Views
Registered: ‎08-08-2017

Re: A partial reconfigurable project with negative WNS and TNS

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I use the partial reconfiguration wizard in version 2017.2 to setup the feature.
I guess what you mean is that I should improve my rise slack first and then do the conversation to the RM. Is it right?
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Voyager
Voyager
2,821 Views
Registered: ‎06-24-2013

Re: A partial reconfigurable project with negative WNS and TNS

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Really depends on your design.

 

Usually partial reconfiguration is not something 'added' at some point to a working design.

I.e. you normally want to make sure that the reconfigurable part is mostly independent from the rest of the design with well defined interfaces (like for example FIFOs or busses).

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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Observer mogarfield
Observer
2,760 Views
Registered: ‎08-08-2017

Re: A partial reconfigurable project with negative WNS and TNS

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Thanks!

 

The bitstream now is running. I have tested a few combinations of configs and I found it really not caused by reconfiguration.

 

Anyway, I am still facing the problem of WNS TNS...... Do you have some suggestions to find the path that causes the negative slack?   

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Voyager
Voyager
5,038 Views
Registered: ‎06-24-2013

Re: A partial reconfigurable project with negative WNS and TNS

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Hey @mogarfield,

 

First I'd check what pathes cause the problem with something like:

report_timing -no_header -path_type summary -max_paths 1000 -slack_lesser_than 0 -setup
report_timing -no_header -path_type summary -max_paths 1000 -slack_lesser_than 0 -hold

Then you inspect the problematic pathes and see if the problem is caused by too deep logic or too much routing delay. The GUI helps there as you can view the Schematic for each path and also the actual routing inside the FPGA.

 

Based on the information gathered, you can usually rearrange or redesign to make it fit.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!

View solution in original post

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