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Explorer
Explorer
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Registered: ‎08-15-2014

About clocks constraints from the same PLL/MMCM

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 HI,

Suppose there are two clocks clk0 and clk1 which is the output from the same MMCM/PLL.

the frequency of clk0= 10Mhz(for example), the frequency of clk1=10Mhz X 15 =150Mhz.

There are data path from both clk0 to clk1 and clk1 to clk0.

For this kind of case:

1. Do I need to do clock domain conversion when using sig1_clk1(which is from clk1) to clock domain clk0? 

2. Do I need to add some special timing constraints for this case, will Vivado tool handle the timing analysis automatically to make sure the data path between clk0 and clk1 could match setup/hold time requirements?

 

For example, sig0_clk0 is from clock domain clk0, sig1_clk1 is from clock domain clk1.

Can I use logic as below without any async-clock domain process, or shall I add some special constraints? will vivado handle this case automatically to ensure correct setup/hold time to match timing analysis?

always @ (posedge clk0 or posedge reset) begin  // process sig0_clk0 in clock domian clk0
if (reset) begin
  sync_edge <=1'b0;
end
else
begin
  if(sig1_clk1) begin ----- here, sig1_clk1 is from clock domain clk1
    sig0_clk0 xxxx <some logics here>
  end
  else
  begin
   sig0_clk0 xxxx <some logics here>
  end
end
end

 

 

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Registered: ‎01-22-2015

Re: About clocks constraints from the same PLL/MMCM

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@jeffson 

The short answer is that Vivado automatically considers all clocks to be synchronous and automatically runs timing analysis on the clock-crossings of data that you describe.  Special timing constraints are not needed to make this happen.

If the clock-crossings do not pass timing analysis then you will need to add circuits and timing constraints that make the crossing successful.  Commonly used circuits are a FIFO (ref: UG473 and PG057) or the handshake synchronizer (ref: XPM_CDC_HANDSHAKE in UG953).

Cheers,
Mark

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238 Views
Registered: ‎01-22-2015

Re: About clocks constraints from the same PLL/MMCM

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@jeffson 

The short answer is that Vivado automatically considers all clocks to be synchronous and automatically runs timing analysis on the clock-crossings of data that you describe.  Special timing constraints are not needed to make this happen.

If the clock-crossings do not pass timing analysis then you will need to add circuits and timing constraints that make the crossing successful.  Commonly used circuits are a FIFO (ref: UG473 and PG057) or the handshake synchronizer (ref: XPM_CDC_HANDSHAKE in UG953).

Cheers,
Mark

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Guide
Guide
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Registered: ‎01-23-2009

Re: About clocks constraints from the same PLL/MMCM

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I will add a caveat.

The different outputs of the same MMCM should be driven on identical clocking resources; i.e. they should all either use a BUFG or they should all use a BUFH, you shouldn't mix and match; different buffer types only exist in the 7 series.

For UltraScale/UltraScale+/Versal, there are only "global" buffers (all the BUFG* are equivalent in terms of propagation delay). However, the clock trees are dynamically built. In order to synchronously cross between different domains from the same MMCM you need to put the clock nets in to the same CLOCK_DELAY_GROUP.

Failure to follow these rules will result in significant clock insertion imbalances between the clock domains which will make it harder for the tool to meet timing; the tool may end up with significant hold times that need fixing and/or you lose significant margin on your setup paths due to this skew.

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