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Adventurer
Adventurer
347 Views
Registered: ‎11-18-2017

Acceptable degree of slack

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Hello,

 

I'm using KCU116 board (in which Kintex UltraScale+ FPGA is embedded) to implement some logics.

After Implementation, my WNS (worse negative slack) is 0.001 (the unit is ns) and WHS (worse hold slack) is 0.012.

Additionally, WPWS (Worst Pulse Width Slack <- I'm not sure what this means) is 0.708.  

TNS (Total Negative Slack), THS (Total Hold Slack) and TPWS (Total Pulse Width Negative Slack) are all 0.

Although my WNS is positive, I'm afraid that 0.001 is not enough for a stable logic (by the way, my clock is 400 Mhz).

I'm just curious about the conventional degree of slack to which it is acceptable (margin).

 

Thanks for your advice.

 

ps. Is it okay to use frequencies like 360, 375, 300 etc other than 250, 500, 400 Mhz? 

(because the former frequencies will yield infinite decimal clock periods and I'm not sure how it could affect the system)

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1 Solution

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Xilinx Employee
Xilinx Employee
292 Views
Registered: ‎05-14-2008

Re: Acceptable degree of slack

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Vivado performs worst case timing analysis.

As long as the design constraints are complete and correct, you can trust a slack of 0.000ns.

There is one thing that could affect those small slacks ---- System Jitter.

This is a factor to evaluate the jitter and noise from the board or system level.

Vivado takes a default system jitter value into account in the timing analysis (the default value varies with device falimies).

But if your design system has more system jitter than default, the 0.000ns slack could actually be negative.

As you're using a Xilinx board, I would expect the default system jitter is enough.

Hardware testing also helps to find any potential issue.

-vivian

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Xilinx Employee
Xilinx Employee
293 Views
Registered: ‎05-14-2008

Re: Acceptable degree of slack

Jump to solution

Vivado performs worst case timing analysis.

As long as the design constraints are complete and correct, you can trust a slack of 0.000ns.

There is one thing that could affect those small slacks ---- System Jitter.

This is a factor to evaluate the jitter and noise from the board or system level.

Vivado takes a default system jitter value into account in the timing analysis (the default value varies with device falimies).

But if your design system has more system jitter than default, the 0.000ns slack could actually be negative.

As you're using a Xilinx board, I would expect the default system jitter is enough.

Hardware testing also helps to find any potential issue.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
Xilinx Employee
Xilinx Employee
289 Views
Registered: ‎05-14-2008

Re: Acceptable degree of slack

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It is ok to use 360, 375, 300 etc.

The timing tool has a significant digits setting. The default value is 3.

For example, for 300MHz, the period is 0.003ns.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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Scholar drjohnsmith
Scholar
288 Views
Registered: ‎07-09-2009

Re: Acceptable degree of slack

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@kimjaewon 

 

One thing to rember,

is the tools run till they meet your constraints, and stop.

so the published 'slack' could well not be for the fastest layout, but it meets your constraints, so it stopped.