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Registered: ‎01-06-2009

Accessing Timing Analyzer for a Core Gen project

I am trying to generate a PCIe Endpoint Block Plus core using the Core Gen wizard. But I get one hold error which I want to eliminate. I use the implement.bat file which does all the steps for me. I dont have to create a ISE project or anything. The only steps I do are create the coreGen project and run the implement.bat. In the output it generates, I can see the following text:


WARNING:Par:62 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in

   your design.


      Review the timing report using Timing Analyzer (In ISE select "Post-Place &

      Route Static Timing Report").  Go to the failing constraint(s) and select

      the "Timing Improvement Wizard" link for suggestions to correct each problem.


   Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to

   ensure the best options are set in the tools for timing closure.


   Use the Xilinx "SmartXplorer" script to try special combinations of

   options known to produce very good results. 


How do I access the Timing analyzer from my project? Or can someone suggest me ways to eliminate the hold error? I have attached the output file.



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Xilinx Employee
Xilinx Employee
Registered: ‎08-02-2007

Re: Accessing Timing Analyzer for a Core Gen project



For this you need to launch Timing Analyser. If using windows, then (Start==>RUN==> timingan.exe). This will ask for ISE project location. Just


click ok.


This will launch the Timing Analyser GUI. Using the GUI File ==> Open design and browse to the location where you have the NCD and PCF.


Using the same GUI use Analyze ==> Analyze against timing constraints and you are done with timing analysis. 


Suggestions to avoid Hold Violation are mentioned in this link



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