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Observer huagangxiaoyan
Observer
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Registered: ‎11-14-2018

Add clock constraints: How to determine input and output delays

Use the constraints wizard in Vivado to add timing constraints.The following parameters are required when setting the input and output delays: tco_min,tco_max,trce_dly_min,trce_dly_max;and tsu,thd.

How to set the values of these parameters, what is the basis for setting these parameter values?

Suppose I am using the Xilinx vc709 development board. Where should I get the information I need?

thank you very much!

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Participant evant_nq
Participant
50 Views
Registered: ‎07-18-2018

Re: Add clock constraints: How to determine input and output delays

Hi huagangxiaoyan,

    So there are multiple types of input and output calculations that you can set for the wizard. These represent how the interface is described.

The basics are Source or System Synchronous. Which says is the relationship relative to the clock at the pin or is it relative to a system clock.

And then there is if the data is relative to the edge of the clock, to the center of the clock, or skew.

(These are all based on what combination you select)

Usually you look at the upstream or downstream devices datasheet and see how they define their requirements. If the clock is forwarded with the data you likely would choose source, otherwise it's likely system synchronous (Which i believe is what you have selected)

The tco_min and tco_max are going to be datasheet values of that interface. Basically how long it's going to be guaranteed valid for so the FPGA knows that it can confirm it sampled the signal in that window.

The trce_dly min/max are going to be related to the board. How long is the delay through those traces from that interface to the FPGA or vise versa.

tsu/thd are going to be the output requirements of that downstream interface. How much setup before the edge, and how much hold after the edge does the data need to be valid relative to a clock edge to meet that devices requirement.

If you arevc709 board, download the board reference design that tests all the on board peripherals.In the constraints files should be the correct input/output constraints to talk to the on board devices without needing to look for the data sheets of those devices to fill in the wizard.

But for anything else, you'll need to find those timing requirements from a datasheet.

 

 

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