Add extra delay without IDELAY primitive

[cesarcf]

Hello,

I want to add a delay of ~4.5 ns to some differential inputs in Kintex US (Vivado 2018.1). I am using 4 IODELAY primitives in cascade mode (with a configuration of IDELAY-ODELAY-IDELAY-ODELAY) to achieve this delay. So far so good.

However, those IOBs that are placed on pin 0 of a "byte group" do not allow a cascade greater than 2 IODELAYs, because delay elements cannot go through the byte boundary. So, I need to add an extra delay in those pins to make up for the 2 IODELAYs I cannot implement. 

My idea is to use a fixed delay as offset and make a fine-tuning with the 2 remaining IODELAYs.

Which is the best way to add that "extra delay" as offset? There is any constraint to determine the delay of a net, or using buffers/LUTs... to get a kind of deterministic delay value?

I also appreciate another suggestion. Thanks in advance!

[drjohnsmith]

Basically , DONT

Analyse why you need such a long delay,
consider registering in the signal,

[cesarcf]

I do need it because the input signals are a data bus with a progressive skew among each line, so I have no option.

Furthermore, a fine adjustment is needed thus if I register the signals the delay will be too higher.

[drjohnsmith]

4.5 ns is one heck of a delay between signals on a bus,

Whats the data rate on the bus ? 

   this is for receive, transmit or both at the FPGA ?

[cesarcf · Accepted solution]

This is for receiving data at up to 600 MHz. It is a great deal of delay but each data line has an accumulative delay and it goes up to 4.5 ns.

I have found a good approach implementing the second pair of IODELAYs coming from user logic and not in a cascaded way directly from an IOB, using the DATAIN input instead of IDATAIN. In this way, I have flexibility to place the IODELAYs as close as possible. 

[drjohnsmith]

Thats doubly amazing. 600 MHz is 1.67 ns per cycle,
thats over two clocks worth of delay....

Wow..