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Visitor dheerendrat
Visitor
69 Views
Registered: ‎05-07-2019

Adding pipeline stages to compensate for routing delay

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Hi,

     Thanks for reading through my query. I want to know if there is a clean way to add pipeline stages in my design.

To provide a background, I am integrating a few custom-IPs acquired from different vendors and integrating with my design on an Ultrascale board. 

So IP 1 is placed at the bottom in X*Y0

IP2 in X0Y4

IP3 in X5Y4

Due to I/O port restrictions not much can be done about these placements and my custom IP design kind of stretches between these 3 IPs. I have freedom to add pipe stages on the interface between IP1(X*Y0)  and my design. How do I add them?

Thanks

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Moderator
Moderator
36 Views
Registered: ‎11-04-2010

Re: Adding pipeline stages to compensate for routing delay

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Hi, @dheerendrat ,

I think in most situations, the placer can balance the timing slack in different pipe stages of resgisters automatiacally. 

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3 Replies
Moderator
Moderator
57 Views
Registered: ‎11-04-2010

Re: Adding pipeline stages to compensate for routing delay

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Hi, @dheerendrat ,

There is no automatical way to add the pipeline register.

You can add the necessary pipeline register in the top level glue logic code.

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Visitor dheerendrat
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47 Views
Registered: ‎05-07-2019

Re: Adding pipeline stages to compensate for routing delay

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Hi hongh,

                Thanks for the suggestion. My only concern is the placement of the pipeline stage registers. Would you have an idea what is going on under the hood while the tool tries to meet timing. Does it look at both sides of the flop to extract slack and optimally use that slack. 

To help you understand my question.

Suppose IP_1_interface --> IP_2_interface timing is not met, so I add N( = 3) pipeline stages in the glue logic i.e.

IP_1_interface --> pipe 1 --> pipe 2 --> pipe 3 --> IP_2_interface

Now there is no logic between pipe 1, pipe  2 and pipe 3, so there is a lot of slack that can be used to accomodate timing requirements between IP_1_interface and pipe 1 and also pipe 3 and IP_2_interface. 

Is the tool capable of doing this analysis over multiple pipeline stages?

Regards

Dheerendra

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Moderator
Moderator
37 Views
Registered: ‎11-04-2010

Re: Adding pipeline stages to compensate for routing delay

Jump to solution

Hi, @dheerendrat ,

I think in most situations, the placer can balance the timing slack in different pipe stages of resgisters automatiacally. 

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Don't forget to reply, kudo, and accept as solution.
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