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Explorer
Explorer
3,813 Views
Registered: ‎07-29-2009

Adding time constraint - false path for BRAM register

I have a set of registers (2D) that are defined like this in Verilog:

       parameter integer NUMBER_OF_SIGNALS     = 8

       localparam integer CHANNELS = (NUMBER_OF_SIGNALS * 4);

       (* ram_style="block" *)
       reg  [13:0]         phaseinc         [0:(CHANNELS-1)];

 

I've seen this and tried it as the starting point:

https://forums.xilinx.com/t5/Vivado-TCL-Community/Setting-false-path-from-an-internal-register/td-p/439620

 

and tried a few different ways,

but I get the error message below:

 

set_false_path from [get_cells -of_objects [get_pins -of_objects [get_nets siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc*] -filter {DIRECTION == OUT}]]

ERROR: [Common 17-165] Too many positional options when parsing 'siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_reg[0][10] siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_reg[0][11] siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_reg[0][12] siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_reg[0][13] siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_reg[0][2] siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_reg[0][3] siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_reg[0][4] siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_reg[0][5] siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_reg[0][6] siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_reg[0][7] siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_reg[0][8] siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_reg[0][9] siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_reg[12][10]

...

 

Any thoughts on how I could specify the phaseinc as a false path since it doesn't change very often in the design?

 

 I've also tried the Timing Constraints editor in Vivado 2016.4:

set_false_path -from [get_pins -hierarchical -filter { PARENT_CELL =~  "*phaseinc*" && DIRECTION == "OUT" }]
 with this message:

Constraints 18.513] set_false_path: list of objects specified for '-from' option contains no valid startpoints....

 

 

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4 Replies
Historian
Historian
3,796 Views
Registered: ‎01-23-2009

Re: Adding time constraint - false path for BRAM register

set_false_path -from [get_cells -of_objects [get_pins -of_objects [get_nets siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc*] -filter {DIRECTION == OUT}]]

 

Did you simply miss the "-" in front of the word "from"?

 

Avrum

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Explorer
Explorer
3,743 Views
Registered: ‎07-29-2009

Re: Adding time constraint - false path for BRAM register

No, the - was there, just pasted in wrong:

set_false_path -from [get_cells -of_objects [get_pins -of_objects [get_nets siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc*] -filter {DIRECTION == OUT}]]
WARNING: [Constraints 18-402] set_false_path: 'siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_i__90' is not a valid startpoint.
Resolution: A valid start point is a main or generated clock pin or port, a clock pin of a sequential cell, or a primary input or inout port. Please validate that all the objects returned by your query belong to this list.
WARNING: [Constraints 18-402] set_false_path: 'siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_i__89' is not a valid startpoint.

...

 

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Historian
Historian
3,725 Views
Registered: ‎01-23-2009

Re: Adding time constraint - false path for BRAM register

With a nested command like this it is very hard to figure out what it is finding - you should run the command interactively and find out what it is matching.

 

But presumably there is a pin of at least one combinatorial cell that is driving a net that matches your wildcard name - we know the cell's name (siggen_jesd_axi_v1_0_S00_AXI_inst/U1/phaseinc_i__90) and since it doesn't end in _reg, we know it is probably not a flip-flop (so the error message is correct).

 

All this being said - I doubt you can do this...

 

If the 2D array is really being implemented as a block RAM (and from the earlier error messages, it isn't clear that it is), then the  phaseinc "registers" no longer exist; they are part of the RAM array. And even if you could find the block RAM, while the contents of the RAM may be pseudo-static, the output port of the RAM will not - it can change every clock depending on the address and read enable of the RAM...

 

Avrum

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Explorer
Explorer
3,715 Views
Registered: ‎07-29-2009

Re: Adding time constraint - false path for BRAM register

Thanks for the reply.  The output of the array is VERY static.  So are you thinking I shouldn't put them in BRAM since they aren't "addressed" and they are vary much a ROM?  I will try removing that declaration and see if it can find them then.

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