After PNR, TNS has very big failure , and Running FPGA, it stops.

[trustfarm]

Hello, previous posting on synthesis.

https://forums.xilinx.com/t5/Timing-Analysis/What-s-difference-on-synthesis-logic-when-TNS-WNS-problem-solve/td-p/964023

After PNR, bitstream generated, but, RUN then FPGA shutdown/reset.

Also, there's Design timing issues. here's snapshot of fault.

It is run on 350Mhz core clock.

How can I resolve it , with incremental way? (for save a pnr time).

[trustfarm]

Also , Power Consume estimation is high, more higher value is TEMP.

Never over 90C.

[trustfarm]

Is it help? on UG949 page 240~ . block retiming strategy?

or is there carry optimization options , when Implentation?

thanks,

[tedbooth]

I recommend that you check out the Xilinx "UltraFast Design Methodology":

https://www.xilinx.com/products/design-tools/ultrafast.html#productAdvantages

Lots of good information on proper design techniques and timing analysis.  When designing for clock rates in the 350 MHz range, it is very important to follow all of the recommendations in order to meet timing.  Proper design will also improve the power consumption.

[drjohnsmith]

You need to re look at your code and code for speed... as tedbooth says, design guides.

[trustfarm]

ok thanks for advices.

we already did  500Mhz , 96% LUT fit, with PCI-e.

Now, we are doing another algorithm, so, there's multiple view of digging.

one of paths rewrite code, 

one of paths case by case treat to run, I need to handle xilinx tool option and handy treatment for Ultrafast workaround.

Is there any option for trial?

thanks, in advance.

[hemangd]

Hi @trustfarm ,

Provide full timing summary report by running report_timing_summary after implementation to evaluate. 

[trustfarm]

thanks for interesting.

Here's full reports.