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Contributor
Contributor
580 Views
Registered: ‎04-13-2018

After PNR, TNS has very big failure , and Running FPGA, it stops.

Hello, previous posting on synthesis.

https://forums.xilinx.com/t5/Timing-Analysis/What-s-difference-on-synthesis-logic-when-TNS-WNS-problem-solve/td-p/964023

 

After PNR, bitstream generated, but, RUN then FPGA shutdown/reset.

Also, there's Design timing issues. here's snapshot of fault.

It is run on 350Mhz core clock.

How can I resolve it , with incremental way? (for save a pnr time).

 

pnr-fail-timing.PNGpnr-fail-timing-detailed.PNG

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I'm a Donde Voy with Poolish.
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7 Replies
Contributor
Contributor
567 Views
Registered: ‎04-13-2018

Re: After PNR, TNS has very big failure , and Running FPGA, it stops.

Also , Power Consume estimation is high, more higher value is TEMP.

Never over 90C.

pnr-fail-powerconsume.PNG

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I'm a Donde Voy with Poolish.
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Contributor
Contributor
552 Views
Registered: ‎04-13-2018

Re: After PNR, TNS has very big failure , and Running FPGA, it stops.

Is it help? on UG949 page 240~ . block retiming strategy?

or is there carry optimization options , when Implentation?

thanks,

 

pnr-fail-b2g-manycarry-11path.PNGpnr-fail-b2g-manycarry-path.PNG

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I'm a Donde Voy with Poolish.
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Voyager
Voyager
551 Views
Registered: ‎03-28-2016

Re: After PNR, TNS has very big failure , and Running FPGA, it stops.

I recommend that you check out the Xilinx "UltraFast Design Methodology":

https://www.xilinx.com/products/design-tools/ultrafast.html#productAdvantages

Lots of good information on proper design techniques and timing analysis.  When designing for clock rates in the 350 MHz range, it is very important to follow all of the recommendations in order to meet timing.  Proper design will also improve the power consumption.

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
Scholar drjohnsmith
Scholar
545 Views
Registered: ‎07-09-2009

Re: After PNR, TNS has very big failure , and Running FPGA, it stops.

You need to re look at your code and code for speed... as tedbooth says, design guides.
Contributor
Contributor
531 Views
Registered: ‎04-13-2018

Re: After PNR, TNS has very big failure , and Running FPGA, it stops.

ok thanks for advices.

we already did  500Mhz , 96% LUT fit, with PCI-e.

Now, we are doing another algorithm, so, there's multiple view of digging.

one of paths rewrite code, 

one of paths case by case treat to run, I need to handle xilinx tool option and handy treatment for Ultrafast workaround.

Is there any option for trial?

thanks, in advance.

 

Founder https://trustcoinmining.com
I'm a Donde Voy with Poolish.
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Moderator
Moderator
487 Views
Registered: ‎03-16-2017

Re: After PNR, TNS has very big failure , and Running FPGA, it stops.

Hi @trustfarm ,

Provide full timing summary report by running report_timing_summary after implementation to evaluate. 

Regards,
hemangd

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Contributor
Contributor
476 Views
Registered: ‎04-13-2018

Re: After PNR, TNS has very big failure , and Running FPGA, it stops.

thanks for interesting.

 

Here's full reports.

 

 

Founder https://trustcoinmining.com
I'm a Donde Voy with Poolish.
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