Any way to specify a timegrp/tnm/etc. inside VHDL/Verilog for ISE?
I have a number of registers which cross clock domains, and need to be set as a false path for timing analysis. If I don't, par goes nuts about "Unusually large hold times" for those signals, and promptly sits there for hours. This is on ISE 14.7.
(Why par does that is another question, but I know TIG-ing the false paths works).
Is there *any* way that I can specify, in VHDL/Verilog, *something* to use in the UCF rather than trying to do it via wildcard matching? That is, something like:
(* TNM = "CROSS_CLOCK" *)
reg this_is_a_crossclock_reg = 0;
or TIMEGRP, or TPTHRU, or anything else? The Xilinx Constraints Guide indicates that none of those can be applied using VHDL/Verilog attributes, but I'm wondering
1) if they work anyway
2) or if there's anything similar that might work
The ASYNC_REG constraint can be applied using VHDL/Verilog but it seems to indicate that's just for simulation.
The normal approach to this is to use TNM_NET to define the set of all synchronous elements that clock on the same clock.
NET "clock_A" TNM_NET = GRP_CLKA ;
NET "clock_B" TNM_NET = GRP_CLKB ;
TIMESPEC TS_A_TO_B = FROM GRP_CLKA TO GRP_CLKB 15 ns DATAPATHONLY ;
I typically use a time based spec rather than TIG for clock crossings, but then use a value large enough to make it easy to meet setup time. DATAPATHONLY prevents hold time analysis.
If you're woried about catching some elements that should not be treated as asynchronous for the same clock crossing, then you could use wildcard matching on net names and try to include some unique string in the names of elements you wanted to TIG.