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Explorer
Explorer
2,789 Views
Registered: ‎04-19-2016

Axi-Stream Interface timing

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Hello,

 

I have an custom IP that works as an cameralink decoder. IP accepts video as cameralink and gives video as Axi-Stream. There an FIFO between the decoded Cameralink side clock and Axi-Stream side. I am using VDMA (S2MM) to write video data to a memory.

I simulated the entire data flow. I hope that I can simulate the one read transaction in the Axi-Stream, from FIFO. But I dont know the Axi-Stream interface timing requirements.

 

  1. What is the Axi-Stream interface timing? 
  2. Does the Axi-Stream timing depends on the VDMA working mode? 

Best Regards,

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Xilinx Employee
Xilinx Employee
4,029 Views
Registered: ‎02-06-2013

Hi

 

It's simple handshaking interface based on tready and tvalid.

 

Refer below doc

 

https://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf

 

https://forums.xilinx.com/t5/DSP-and-Video/Understanding-Video-AXI-Stream-Custom-IP/td-p/751844

 

Regards,

Satish

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Xilinx Employee
Xilinx Employee
4,030 Views
Registered: ‎02-06-2013

Hi

 

It's simple handshaking interface based on tready and tvalid.

 

Refer below doc

 

https://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf

 

https://forums.xilinx.com/t5/DSP-and-Video/Understanding-Video-AXI-Stream-Custom-IP/td-p/751844

 

Regards,

Satish

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Explorer
Explorer
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Registered: ‎04-19-2016
Hello @yenigal,

Thank you.

Regards,
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Explorer
Explorer
2,709 Views
Registered: ‎04-19-2016
Hello Again,

But I want to ask something. Which one( tvalid, tready) should be asserted firstly?

I connected Tready to fifo read enable. And connected fifo valid flag to the Tvalid. In this schema, after the one clock Tready is asserted, tvalid will be asserted. This is problem?

Best Regards,
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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @doner_t,

 

There is no requirement about this.

 

The master can be ready before the slave (tvalid first) or the slave can be ready before the master (tready first).

 

You just have to know that a data has been sent if both tready and tvalid are high. So the master should send the next sample in the next clock rising edge.

 

Hope that clarifies,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Explorer
Explorer
2,679 Views
Registered: ‎04-19-2016

Hello @florentw,

 

Thank you for explaining the hand-shaking mechanism in the Axi-Stream interface. Because of Tready (coming from Slave) signal is connected to the FIFO read_enable pin, Tvalid&Tready hand-shaking mechanism is automatically took place here. 

 

Regards, 

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