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Newbie catbagan
Newbie
761 Views
Registered: ‎09-25-2018

BUFGCE Skew and Timing Issue

Hello,

I am struggling achieving timing closure and welcome any advice.

My design targetting a Virtex UltraScale (vu095) FPGA uses 4 gated 322MHz clocks. The design instantiates an MMCM to generate a single 322MHz clock. This clk322 is the input to the 4 BUFGCE's and also goes through a BUFG to synchronize the clock enable signals. The 4 BUFGCE's and BUFG are in parallel.

The path from the flip-flop that synchronizes the clock enable to the CE pin of the BUFGCE is failing timing for all 4 BUFGCE's. The timing report shows a large negative skew which causes the path to fail even though the data path delay is reasonable. Here is the report for 1 of these paths.

 

Slack (VIOLATED) :        -0.162ns  (required time - arrival time)
  Source:                 u_oem/u_clk_322/gen_bs_nce[0].u_bs_nce/q1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm322p38  {rise@0.000ns fall@1.551ns period=3.102ns})
  Destination:            u_oem/u_clk_322/u_bufgce322_0/CE
                            (rising edge-triggered cell BUFGCE clocked by mmcm322p38  {rise@0.000ns fall@1.551ns period=3.102ns})
  Path Group:             mmcm322p38
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.102ns  (mmcm322p38 rise@3.102ns - mmcm322p38 rise@0.000ns)
  Data Path Delay:        0.522ns  (logic 0.118ns (22.605%)  route 0.404ns (77.395%))
  Logic Levels:           0  
  Clock Path Skew:        -2.530ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.393ns = ( 7.495 - 3.102 ) 
    Source Clock Delay      (SCD):    6.973ns
    Clock Pessimism Removal (CPR):    0.051ns
  Clock Uncertainty:      0.110ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.209ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.392ns (routing 0.335ns, distribution 2.057ns)
  Clock Net Delay (Destination): 0.372ns (routing 0.076ns, distribution 0.296ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm322p38 rise edge)
                                                      0.000     0.000 r  
    AW18                                              0.000     0.000 r  I_REFCLK_1944M_FPGA_P (IN)
                         net (fo=0)                   0.000     0.000    u_clk19p44_ibuf/I
    HPIOBDIFFINBUF_X1Y34 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.530     0.530 r  u_clk19p44_ibuf/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.090     0.620    u_clk19p44_ibuf/OUT
    AW18                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.620 r  u_clk19p44_ibuf/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.750     1.370    buf_clk19p44_h
    BUFGCE_X1Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     1.453 r  u_clk19p44_bufg/O
                         net (fo=1746, routed)        2.839     4.292    u_oem/u_clk_322/u_clk_wiz/inst/i_clk19p44
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     4.061 r  u_oem/u_clk_322/u_clk_wiz/inst/mmcme3_adv_inst/CLKOUT0
                         net (fo=5, routed)           0.437     4.498    u_oem/u_clk_322/mmcm322p38
    BUFGCE_X1Y70         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     4.581 r  u_oem/u_clk_322/u_bufg322/O
    X3Y2 (CLOCK_ROOT)    net (fo=8, routed)           2.392     6.973    u_oem/u_clk_322/gen_bs_nce[0].u_bs_nce/bbstub_o_clk322p38
    SLICE_X87Y151        FDRE                                         r  u_oem/u_clk_322/gen_bs_nce[0].u_bs_nce/q1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y151        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.118     7.091 r  u_oem/u_clk_322/gen_bs_nce[0].u_bs_nce/q1_reg/Q
                         net (fo=1, routed)           0.404     7.495    u_oem/u_clk_322/CE
    BUFGCE_X1Y64         BUFGCE                                       r  u_oem/u_clk_322/u_bufgce322_0/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm322p38 rise edge)
                                                      3.102     3.102 r  
    AW18                                              0.000     3.102 r  I_REFCLK_1944M_FPGA_P (IN)
                         net (fo=0)                   0.000     3.102    u_clk19p44_ibuf/I
    HPIOBDIFFINBUF_X1Y34 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.333     3.435 r  u_clk19p44_ibuf/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.051     3.486    u_clk19p44_ibuf/OUT
    AW18                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     3.486 r  u_clk19p44_ibuf/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.649     4.135    buf_clk19p44_h
    BUFGCE_X1Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     4.210 r  u_clk19p44_bufg/O
                         net (fo=1746, routed)        2.578     6.788    u_oem/u_clk_322/u_clk_wiz/inst/i_clk19p44
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     7.123 r  u_oem/u_clk_322/u_clk_wiz/inst/mmcme3_adv_inst/CLKOUT0
    X3Y2 (CLOCK_ROOT)    net (fo=5, routed)           0.372     7.495    u_oem/u_clk_322/mmcm322p38
    BUFGCE_X1Y64         BUFGCE                                       r  u_oem/u_clk_322/u_bufgce322_0/I
                         clock pessimism              0.051     7.545    
                         clock uncertainty           -0.110     7.435    
    BUFGCE_X1Y64         BUFGCE (Setup_BUFCE_BUFGCE_I_CE)
                                                     -0.101     7.334    u_oem/u_clk_322/u_bufgce322_0
  -------------------------------------------------------------------
                         required time                          7.334    
                         arrival time                          -7.495    
  -------------------------------------------------------------------
                         slack                                 -0.162    

 

In my .xdc constraints, I am doing

set_property LOC MMCME3_ADV_X1Y2 [get_cells {u_oem/u_clk_322/u_clk_wiz/inst/mmcme3_adv_inst}]

set_property USER_CLOCK_ROOT X3Y2 [get_nets -of_objects [get_pins {u_oem/u_clk_322/u_bufg*322*/O}]]

Additional notes:

  • Using Vivado 2017.3.1
  • LUTS utilization of the design is <20%
  • Design meets timing consistently when targetting Virtex UltraScalePlus (vu7p)
  • The logic driven by the gated clocks do not fit in one clock region so I cannot use a BUFHCE

 

What else can I do to reduce the clock path skew? In the timing report towards the end, what is "clock uncertainty" and "BUFGCE (Setup_BUFCE_BUFGCE_I_CE)"?

Thank you for reading.

 

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1 Reply
714 Views
Registered: ‎01-22-2015

Re: BUFGCE Skew and Timing Issue

@catbagan

Welcome to the Xilinx Forum!

     My design targetting a Virtex UltraScale (vu095)…
Wow!  That’s serious power and $$.

     …path from the flip-flop … to the CE pin of the BUFGCE is failing timing for all 4 BUFGCE's
If you have a single flip-flip feeding all 4 CE pins then you might try replicating-in-parallel the flip-flop. That is, each BUFGCE will be fed by a separate flip-flop. Implementation can then move these flip-flops around to help solve the timing analysis failure you are seeing. Implementation can be told to do flip-flop replicating-in-parallel for you or you can do it manually.

     set_property LOC MMCME3_ADV_X1Y2 …     
     set_property USER_CLOCK_ROOT X3Y2 …
These constraints give specific locations within the FPGA for the MMCM and the USER_CLOCK_ROOT.  It is often best (for many reasons – including timing analysis) to let Vivado implementation handle all location decisions.  So, you might try commenting out these constraints.

     In the timing report towards the end, what is "clock uncertainty"..
This is uncertainty in time for the clock launch-edge and clock capture-edge of the timing path. I believe this uncertainty is dominated by clock jitter. See UG906, page 224 for more information on clock uncertainty.

    what is … "BUFGCE (Setup_BUFCE_BUFGCE_I_CE)"?
This is the setup requirement for the BUFGCE, which says that the signal at the CE-pin signal must be stable for 0.101ns before a clock rising-edge occures at the I-pin. For more information see parameter, T(BCCCK_CE), in Fig 2-19 (on about page 30) of UG572.

Cheers,
Mark

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