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654 Views
Registered: ‎01-22-2015

BUFIO+BUFR input interface constraints

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Three typical ways to design the clocking structure for an input interface are described <here> by Avrum.

 

I am trying to implement the “Direct Capture with BUFIO” structure as shown below, where:

  • port, DCLK1, is a clock-capable pin
  • register, DATA1_IOB, is packed into the IOB
  • register, DATA1_FAB, is in the FPGA fabric and in the same clocking region as the BUFR

BUFR_BUFIO.jpg

I have written the following constraints for the interface:

create_clock -period 20 [get_ports DCLK1]
set_input_delay -clock DCLK1 -max 11.0 [get_ports DATA1]
set_input_delay -clock DCLK1 -min 9.0 [get_ports DATA1]

  

I understand that a create_generated_clock constraint is autogenerated for output of the BUFR (ug903, pg88).

 

Do I need a create_generated_clock constraint for the output of the BUFIO?

 

Are other constraints needed for this interface – perhaps something for the clock-crossing from DATA1_IOB to DATA1_FAB?

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Xilinx Employee
Xilinx Employee
865 Views
Registered: ‎05-06-2008

Re: BUFIO+BUFR input interface constraints

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Hello markg@prosensing.com,

 

You do not need a create_generated_clock on the output of the BUFIO component.  The timing engine will propagate the clocking definition downstream through the BUFIO component to the synchronous elements.  The cross clock domain path between the BUFIO clock domain and the BUFR clock domain will be analyzed by the timing engine and be included in the timing analysis (report_timing_summary).  

 

Please let me know if you have any other questions.


Thanks,
Chris

2 Replies
Xilinx Employee
Xilinx Employee
866 Views
Registered: ‎05-06-2008

Re: BUFIO+BUFR input interface constraints

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Hello markg@prosensing.com,

 

You do not need a create_generated_clock on the output of the BUFIO component.  The timing engine will propagate the clocking definition downstream through the BUFIO component to the synchronous elements.  The cross clock domain path between the BUFIO clock domain and the BUFR clock domain will be analyzed by the timing engine and be included in the timing analysis (report_timing_summary).  

 

Please let me know if you have any other questions.


Thanks,
Chris

Historian
Historian
614 Views
Registered: ‎01-23-2009

Re: BUFIO+BUFR input interface constraints

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Do I need a create_generated_clock constraint for the output of the BUFIO?

 

Are other constraints needed for this interface – perhaps something for the clock-crossing from DATA1_IOB to DATA1_FAB?

 

No. No additional constraints are required.

 

A clock propagates through a buffer (like a BUFG or a BUFIO), and in fact will also propagate through a BUFR (which is the right thing to do if the BUFR is in pass-through or divide_by_1 mode).

 

When you place a clock on a net or pin that already has a clock, then the new clock overrides the old one (unless the -add option is used, in which case the pin/net carries both clocks). So the automatically generated clock created on the output of the BUFR overrides the input clock that would otherwise propagate through the BUFR.

 

The paths between the FFs from the BUFIO clock to the BUFR clock are normal synchronous timing paths. They should specifically not have any exceptions on them, as the tool needs to analyze the paths properly including the clock skew between the BUFIO and BUFR clock.

 

Avrum