11-08-2017 10:40 AM
I am using an ISERDES with a BUFIO for the high speed clock and a BUFR for the parallel clock. In the 7 series manual it says the the two clocks to the ISERDES should ideally be in phase. I dont really understand how this can happen when using these two buffers. Can someone explain please. Thanks
11-08-2017 10:51 AM
Take a look here:
The BUFIO/BUFR arrangement usuallly looks like the picture attached.
Also pay attention to the rules in UG471:
The only valid clocking arrangements for the ISERDESE2 block using the networking
interface type are:
• CLK driven by BUFIO, CLKDIV driven by BUFR
• CLK driven by MMCM or PLL, CLKDIV driven by CLKOUT[0:6] of same MMCM or
When using a MMCM to drive the CLK and CLKDIV of the ISERDESE2, the buffer types
suppling the ISERDESE2 can not be mixed. For example, if CLK is driven by a BUFG, then
CLKDIV must be driven by a BUFG as well. Alternatively, the MMCM can drive the
ISERDESE2 though a BUFIO and BUFR.
11-08-2017 10:53 AM
BUFG, BUFR, BUFIO
Are phase matched. So if you follow the example designs, the clocks go through global, or regional, or IO region, phase matched global clock buffers, to the ISERDES/OSERDES.
11-08-2017 11:49 AM
To drive the CLK and CLKDIV of an ISERDES there are only a few and very specific clock structures that meet the needs of the ISERDES. The BUFIO/BUFR combination in the same clock region is one of them. You are right that the two buffers will not result in "identical phase" at the ISERDES, but, nonetheless, this is a correct and supported clocking structure that ensures that the phase requirements between CLK and CLKDIV are met (whatever they "really" are).
11-08-2017 11:56 AM
11-08-2017 12:35 PM
OK I accept that the documented method does work. But I am trying to get a 12 bit design to work using two ISERDES, one for the p and one for the n using SDR mode. But for some reason I am finding that the n data is delayed onto the other clock edge. I am clocking the n using an inverted clock so I dont really understand why this is happening.
The p ISERDES CLK is clocked using the BUFIO clock
The n ISERDES CLK is clocked using the BUFIO clock inverted
The p ISERDES data is the p input data
The n ISERDES data is the n input data
The CLKDIV is from a BUFR
The BUFIO clock is 150MHz
The BUFR clock is 25MHz
11-08-2017 12:56 PM
11-08-2017 01:03 PM
11-08-2017 01:12 PM
As far as I know, what you are describing is illegal... In the example you are using, the _n ISERDES has its CLK 180 degrees out of phase with the rising edge of CLKDIV (which violates the "phase aligned" requirement of the ISERDES).
The normal way to do this would be a single ISERDES in DDR mode, but the ISERDES (for a reason I have never been able to understand, nor has ever been adequately explained to me) does not support 12:1...
So, you will need to do something intermediate - use the ISERDES for 6:1 DDR deserialization to a CLKDIV that is twice the rate of your 12 bit data (CLK/3). Then do the 2:1 deserialization in the fabric. This needs a third clock, (CLK, CLK/3 and CLK/6), with no obvious way of generating the third one (at least not with the BUFIO/BUFR). This is, admittedly, a pain - you will need to do something with a global clock...
One solution would be to gather two 6 bit samples into a single 12 bit sample and push it into a clock crossing FIFO on every other clock of the BUFR clock. You can then bring the BUFR clock to an MMCM to generate the proper /6 clock and use that to pop the data from the clock crossing FIFO...
That being said, at 150MHz, the ISERDES isn't necessary - you can simply clock the data directly in an IDDR at 150MHz DDR, and then do the complete 6:1 deserialization in the fabric. The only time the ISERDES is "needed" is when the CLK rate is too high to work with in the fabric...
11-08-2017 01:21 PM
11-08-2017 01:45 PM
I can use a MMCM for the clocks so it wont be an issue generating the 50MHz clock. I may be able to use an IDDR but I am only using an Artix so I guess that 150MHz might be pushing it a bit for the logic.
Not really. Even Artix should be able to do a fair amount of stuff at 150MHz. But to be clear, your actual "word" period is 25MHz - 150MHz DDR is 300Mbps. Divide that by 12 and we get one 12 bit word every 25MHz clock. So if you wanted to use the ISERDES, you would use 150MHz on the BUFIO and 50MHz on the BUFR (/3), and then take the 50MHz and divide it by 2 in the MMCM (or use a BUFGCE).
Depending on the timing, though, you might just be able to take the 150MHz to an MMCM and use CLKOUT0 to generate the clock for the IDDR. This has "worse" timing than using the BUFIO, but at 150MHz DDR, it can work (we need to know the timing characteristics of the input interface). The same MMCM can generate the 25MHz clock - it will be no problem to do the 6:1 deserialization (and framing) at the 150MHz clock rate, then transfer the 12 bit words directly to the 25MHz domain. If you use BUFGs on both clocks, you can pass data synchronously between the domains (no FIFO is needed). Furthermore, the MMCM has the fine phase shifting capability, which allows you to choose the "perfect" clock phase to capture the incoming data.
The last combination - taking the clock directly to the MMCM, which will generate a 150MHz clock for the ISERDES.CLK, a 50MHz for the ISERDES.CLKDIV (which is legal) and another clock at 25MHz is probably not necessary...