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yanqil
Newbie
Newbie
11,131 Views
Registered: ‎01-10-2014

Barely failing timing constraint. Need help

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Hi, I don't have much experience with timing constraints and need some pointers.  The design is barely missing timing constraints.  Error message is attached below.  Several questions here:

1. How to resolve this issue?

2. I am a little confused with the error message. I assume either the fs_x1 or fs_x2 clock signals are not meeting timing, but why are the soure and destination signals referred to in the error message (rst_fade_engine_array and addr_rd_p1) completely not related to clocking?

3. SLICE_X130Y189.SR    net has fanout of 591 and the bulk of the delay.  Is the large fanout the reason for the timing not being met?

 

Please help and please excuse my lack of knowledge in this field.

 

Thank you.

 

Yan

 

 

Timing constraint: TS_clk_top_i0_clock_i0_clkout1 = PERIOD TIMEGRP "clk_top_i0_clock_i0_clkout1"         TS_FS_PAD / 2 HIGH 50%;
  13152 paths analyzed, 13152 endpoints analyzed, 8 failing endpoints
  8 timing errors detected. (8 setup errors, 0 hold errors, 0 component switching limit errors)
  Minimum period is   3.266ns.
 --------------------------------------------------------------------------------
 
 Paths for end point ForImplementation.Generate_2path_fading[11].two_path_fading_inst/addr_rd_p1_0 (SLICE_X130Y189.SR), 1 path
 --------------------------------------------------------------------------------
 Slack (setup path):     -0.011ns (requirement - (data path - clock path skew + uncertainty))
   Source:               rst_fade_engine_array_5 (FF)
   Destination:          ForImplementation.Generate_2path_fading[11].two_path_fading_inst/addr_rd_p1_0 (FF)
   Requirement:          3.255ns
   Data Path Delay:      2.793ns (Levels of Logic = 0)
   Clock Path Skew:      -0.287ns (3.109 - 3.396)
   Source Clock:         fs_x1 rising at 0.000ns
   Destination Clock:    fs_x2 rising at 3.255ns
   Clock Uncertainty:    0.186ns
 
   Clock Uncertainty:          0.186ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter (TSJ):  0.070ns
     Discrete Jitter (DJ):       0.110ns
     Phase Error (PE):           0.120ns
 
   Maximum Data Path at Slow Process Corner: rst_fade_engine_array_5 to ForImplementation.Generate_2path_fading[11].two_path_fading_inst/addr_rd_p1_0
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
     SLICE_X91Y175.DQ     Tcko                  0.337   rst_fade_engine_array_5
                                                        rst_fade_engine_array_5
     SLICE_X130Y189.SR    net (fanout=591)      2.001   rst_fade_engine_array_5
     SLICE_X130Y189.CLK   Tsrck                 0.455   ForImplementation.Generate_2path_fading[11].two_path_fading_inst/addr_rd_p1(8)
                                                        ForImplementation.Generate_2path_fading[11].two_path_fading_inst/addr_rd_p1_0
     -------------------------------------------------  ---------------------------
     Total                                      2.793ns (0.792ns logic, 2.001ns route)
                                                        (28.4% logic, 71.6% route)
 
 --------------------------------------------------------------------------------
 
 Paths for end point ForImplementation.Generate_2path_fading[11].two_path_fading_inst/addr_rd_p1_3 (SLICE_X130Y189.SR), 1 path
 --------------------------------------------------------------------------------
 Slack (setup path):     -0.011ns (requirement - (data path - clock path skew + uncertainty))
   Source:               rst_fade_engine_array_5 (FF)
   Destination:          ForImplementation.Generate_2path_fading[11].two_path_fading_inst/addr_rd_p1_3 (FF)
   Requirement:          3.255ns
   Data Path Delay:      2.793ns (Levels of Logic = 0)
   Clock Path Skew:      -0.287ns (3.109 - 3.396)
   Source Clock:         fs_x1 rising at 0.000ns
   Destination Clock:    fs_x2 rising at 3.255ns
   Clock Uncertainty:    0.186ns
 
   Clock Uncertainty:          0.186ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter (TSJ):  0.070ns
     Discrete Jitter (DJ):       0.110ns
     Phase Error (PE):           0.120ns
 
   Maximum Data Path at Slow Process Corner: rst_fade_engine_array_5 to ForImplementation.Generate_2path_fading[11].two_path_fading_inst/addr_rd_p1_3
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
     SLICE_X91Y175.DQ     Tcko                  0.337   rst_fade_engine_array_5
                                                        rst_fade_engine_array_5
     SLICE_X130Y189.SR    net (fanout=591)      2.001   rst_fade_engine_array_5
     SLICE_X130Y189.CLK   Tsrck                 0.455   ForImplementation.Generate_2path_fading[11].two_path_fading_inst/addr_rd_p1(8)
                                                        ForImplementation.Generate_2path_fading[11].two_path_fading_inst/addr_rd_p1_3
     -------------------------------------------------  ---------------------------
     Total                                      2.793ns (0.792ns logic, 2.001ns route)
                                                        (28.4% logic, 71.6% route)
 
 --------------------------------------------------------------------------------

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sampatd
Scholar
Scholar
18,372 Views
Registered: ‎09-05-2011
Since the slack is very less. You might want to use smartXplorer tool to help achieve timing closure:
http://www.xilinx.com/support/documentation/white_papers/wp287.pdf

If that doesn't help, refer to section "Designs with high fanout" on page 235 of:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug612.pdf

View solution in original post

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6 Replies
sampatd
Scholar
Scholar
18,373 Views
Registered: ‎09-05-2011
Since the slack is very less. You might want to use smartXplorer tool to help achieve timing closure:
http://www.xilinx.com/support/documentation/white_papers/wp287.pdf

If that doesn't help, refer to section "Designs with high fanout" on page 235 of:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug612.pdf

View solution in original post

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brucey
Xilinx Employee
Xilinx Employee
11,101 Views
Registered: ‎03-24-2010

Try different cost table to see if tool can close timing.

Or you can try to duplicate your reset register(rst_fade_engine_array_5).

Regards,
brucey
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yanqil
Newbie
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11,096 Views
Registered: ‎01-10-2014

Tried using smart explorer with cost tables 1-40 and it turns out I am already using the cost table with the lowest timing score.  Duplicating the register seemed to have created timing issues elsewhere.  Also, placing a max-fanout attribute on the signal created even more timing constraint failures elsewhere.  Will keep trying.  Any other ideas will be appreciated.

 

Thanks.

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graces
Moderator
Moderator
11,083 Views
Registered: ‎07-16-2008

This is a cross domain clock path.

 Source Clock:         fs_x1 rising at 0.000ns 
Destination Clock:    fs_x2 rising at 3.255ns

 

Please firstly ensure he requirement (3.255ns) matches the actual need.

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brucey
Xilinx Employee
Xilinx Employee
11,071 Views
Registered: ‎03-24-2010

Try reconfig CMT(clocking wizard) to get one configuration that has minimum jitter.

Regards,
brucey
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yanqil
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Registered: ‎01-10-2014

A combination of the built-in strategies and the cost table did it.  Thanks everyone.

 

Yan

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