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999068709169
Explorer
Explorer
10,354 Views
Registered: ‎09-08-2009

Basic OFFSET out question

When I set "offset out" contraint => Too much delay difference from registers to output pads?

 

 

NET "InClk" TNM_NET = "InClk";
TIMESPEC TS_InClk = PERIOD "InClk" 12.5 ns HIGH 50 %;
TIMEGRP "OutData"= PADS("o_Data[0]" "o_Data[1]" "o_Data[2]"); TIMEGRP "OutData" OFFSET = OUT 12 ns AFTER "InClk" REFERENCE_PIN "OutClk" RISING;

 

Extra Information:

I have a source synchronous FPGA data and clock output that I want a fixed relationship

I send the clock using ODDR2, I register the data just before pad.

I want to have a fixed delay :

from several synchronous data registers ------------------------> to the pad (FPGA data outputs)

When I do this I see to much delay difference from the registers (just before the pads) to output pads in trace report.

 

Clock Structure:

InClk ----> PLL ----> clk_80mhz -------> OutClk through ODDR2

                                              -------> Registers (Internal register just before pad)

 

 

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2 Replies
999068709169
Explorer
Explorer
10,346 Views
Registered: ‎09-08-2009

I am using Spartan 6 100 and PlanAhead 14,6

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graces
Moderator
Moderator
10,328 Views
Registered: ‎07-16-2008

Did you place the data registers into IOB? That will ensure a more fixed delay than the slice registers.

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