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barco2
Adventurer
Adventurer
812 Views
Registered: ‎02-13-2009

Building bitstream for multiple speed grades

Hi,

after building a bitstream for a -1 speed grade I can easily check with an additiional timing report, if the same bitstream also matches timing in a -2 speed grade device. However, for a critical design this will most likely reveal some hold time failures for the slow bitstream in a faster device.

Is it possible to let the router optimize timing for both the slower -1 and the faster -2 speed grade? I.e. setup times should be checked against -1 device and hold times against -2 device...?

Thanks
Martin

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5 Replies
lowearthorbit
Scholar
Scholar
789 Views
Registered: ‎09-17-2018

b2,

Xilinx will only guarantee operation when the bitstream build matches the device.  No other build is supported.

lowearthorbit

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barco2
Adventurer
Adventurer
715 Views
Registered: ‎02-13-2009


@lowearthorbit wrote:

Xilinx will only guarantee operation when the bitstream build matches the device.  No other build is supported.

You are absolutely right. But one has to get creative as Xilinx lead times are already exceeding 20 weeks with the US/China trade war having just started.

Being able to run a bitstream on multiple speed grades would allow procurement greater flexibility in buying the chips they can get and not just the ones that have been targeted.

Cheers
Martin

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drjohnsmith
Teacher
Teacher
686 Views
Registered: ‎07-09-2009

I see the idea,
you might want to check,
I remember a while back some post similar, the problem was the programmer / chip were to clever, and the file for the slower part could not be programmed into the faster part.

I can't find it, it might have been a CPLD, but give it a go with what you have ,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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barco2
Adventurer
Adventurer
644 Views
Registered: ‎02-13-2009

I think I found a solution: one can simply add more hold slack by adding a "set_clock_uncertainty -hold" constraint. After implementation a manual timing report for the faster speed grade but without the uncertainty constraint should then be run for verification. This can prove the additional hold slack in the design is enough for the slow bitstream to also match hold times of the faster device.

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625 Views
Registered: ‎01-22-2015

This can prove the additional hold slack in the design is enough for the slow bitstream to also match hold times of the faster device.

Don't do this!

Instead,

  • Use Vivado to generate bitstream#1 for -1 speed-grade device
  • Use Vivado to generate bitstream#2 for -2 speed-grade device
  • If you can only buy -1 speed-grade device then only use bitstream#1
  • If you can only buy -2 speed-grade device then only use bitstream#2

 

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