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Bus cdc and asyn_reg attribute

Adventurer
Posts: 95
Registered: ‎11-09-2009

Bus cdc and asyn_reg attribute

[ Edited ]

Hi,

In the following pseudo-example:

1)Is the ASYNG_REG needed only to

capture_cdc1 and capture_cdc2 ?

2)Do "capture_cdc3" and "data_out" need the ASYNC_REG attribute ?

 

 

Data_in 8-bit   --clk1

capture_in : single-bit --clk1

Data_out  : 8-bit data_out clk2

 

--clk2

capture_cdc1<=capture_in;

capture_cdc2<=capture_cdc1;

capture_cdc3<=capture_cdc2;

If capture_cdc2='1' and capture_cdc3='0' then

data_out<=data_in;

 

Teacher
Posts: 9,030
Registered: ‎08-14-2007

Re: Bus cdc and asyn_reg attribute

I'm assuming that the capture_in signal indicates that the data_in is valid.  If so, then presumably you can build an interface where the clock enable for data_out is only active when data_in is known to be valid.  In that case, you can theoretically come up with minimum setup and hold to the clk2 cycle where the enable is valid, and therefore treat data_in as synchronous to clk2.

 

By the way, I assume you meant to write:

 

If capture_cdc2='1' and capture_cdc3='0' then

 

-- Gabor
Teacher
Posts: 3,339
Registered: ‎01-23-2009

Re: Bus cdc and asyn_reg attribute

(aside from the typo noted by @gszakacs) Your synchronizer is a good start.

 

Yes, you should have ASYNC_REG on capture_cdc1 and capture_cdc2, but not on capture_cdc3 (since that isn't part of the metastability chain).

 

But this is not sufficient...

 

First, you need to make sure that both capture_cdc and data_in come directly from flip-flops.

 

Next, you need an exception on the paths that cross between the two clock domains - both the paths from capture_cdc to capture_cdc1 as well as the paths from data_in to data_out. Normally this should be a set_max_delay -datapath_only. The value of the constraint and the speed of the CDC (how many events they can cross per second), but generally one uses the smaller of the two clock periods of clk1 and clk2.

 

For more on constraining clock domain crossing circuits, take a look at this post on CDC constraints (as well as the posts referenced in that post).

 

Avrum

Adventurer
Posts: 95
Registered: ‎11-09-2009

Re: Bus cdc and asyn_reg attribute

[ Edited ]

Hi,

Thanks.

Yes, it was a typo.

And the constrains are OK, as like you said.

 

ASYNC_REG goes only to _cdc1 and _cdc2,

no anywhere else, not to data either ?

 

Teacher
Posts: 9,030
Registered: ‎08-14-2007

Re: Bus cdc and asyn_reg attribute

Yes that's correct.  _cdc3 is not a clock domain crossing.  It is just a delay element for edge detection.  _cdc2 is considered to be already on the clk2 domain and free from metastability (it actually has a really tiny chance of metastability).  data_in, assuming it is known to be stable during the cycle when _cdc2 is high and _cdc3 is low, is not considered asynchronous to clk2, so it also does not get the ASYNC_REG attribute.

-- Gabor
Visitor
Posts: 13
Registered: ‎10-06-2016

Re: Bus cdc and asyn_reg attribute

I think that _cdc1 and _cdc2 needs to be declare as a vector with a ASYNC_REG declaration. By doing that _cdc1 and _cdc2 will be place in the same slice.
Adventurer
Posts: 95
Registered: ‎11-09-2009

Re: Bus cdc and asyn_reg attribute

Hi lior.glass.,

Could you be more psecific what you mena by

"declare as a vector" here ?

>declare as a vector with a ASYNC_REG declaration

 

 

Highlighted
Teacher
Posts: 9,030
Registered: ‎08-14-2007

Re: Bus cdc and asyn_reg attribute

I assume he means something like:

 

signal capture_cdc : std_logic_vector (2 downto 1);

 

This would allow you to declare both with ASYNC_REG attribute in one line, however it shouldn't be necessary to ensure the two flops are placed together.  Any two connected ASYNC_REG flops should be placed near each other.

-- Gabor