05-30-2019 04:32 PM
I am trying to solve a CDC error by using a 2 Flip Flop synchronizer technique as shown below. But Vivado is not recognizing it as a CDC circuit and flagging an error for the first Flip Flop which is signal1.
attribute ASYNC_REG : string;
attribute ASYNC_REG of signal1: signal is "TRUE";
attribute ASYNC_REG of signal2: signal is "TRUE";
CDC_sync: process(clk) begin
if rising_edge(clk) then
signal1 <= in_signal;
signal2 <= signal1;
Thanks in advance.
05-31-2019 12:21 AM
What error did you receive about signal1?
05-31-2019 08:49 AM
Thanks for the response. I get the following warning when I run report clock interaction
|Name||Slack||Levels||High Fanout||From||To||Total Delay||Logic Delay||Net Delay||Logic %||Net %||Requirement||Source Clock||Destination Clock||Exception||Skew|
|Constrained Paths (1)|
05-31-2019 08:56 AM
All data crossings are assummed synchronous by default, so you must exclude the clock domain crossing path with a constraint. Then your timing error will go away.
06-03-2019 12:52 PM
As indicated by lowearthorbit, all clocks are related by default. Using sync flops with "ASYNC_REG" property would tell the tool to place the two flops in the same CLB. You still need to add a false path constraint to the signal1 flop.
06-03-2019 02:18 PM
You still need to add a false path constraint to the signal1 flop
Careful - "You still need to add an exception to the path ending at the signal1 flop". The correct exception isn't always a "set_false_path" - depending on the characteristics of the clock domain crossing circuit, it may need to be a "set_max_delay -datapath_only"...
06-03-2019 02:43 PM
Can I use XPM_CDC_SINGLE so that Vivado can recognize it as a synchronizer solution for CDC and will not flag critical warning for signal1.
06-04-2019 07:47 AM