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Visitor marwise
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10,965 Views
Registered: ‎02-26-2016

CDC analysis (AXI Quad SPI core v 3.2)

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Hello,
this is my first post here, thank you in advance for any help you could offer!

In my current project, an Ultrascale FPGA talks to a CPU over a SPI interface. FPGA is the slave, CPU is the master.

I started with "AXI Quad SPI" core v 3.2 (Xilinx IP, Vivado 2015.4) example design having:
- standard mode, slave configuration
- by default ext_spi_clk and axi_clk synchronous.
After Syntesis, I run CDC analysis: no CDC error (as there's only one clock domain).

Then I enabled "async clock mode" since the axi clock and the ext_spi_clk are not synchronous in my real project.
After Synthesis, I run CDC analysis: various warning and critical warnings pop up.

They are basically of 3 types (at the end of the post, you can find the full list):

 

ID      Severity  Description                                         
------  --------  --------------------------------------------------        
CDC-2   Warning   1-bit synchronized with missing ASYNC_REG property  
CDC-10  Critical  Combinatorial logic detected before a synchronizer
CDC-15  Warning   Clock enable controlled CDC structure detected 


CDC-xy codes are described in UG906, Design Analysis and Closure Techniques.

My questions:

1) should I declare the two clocks as asynchronous? Or should I keep the original constraints (e.g., false path) provided by the core (which would get overruled by the set_clock_groups -asynchronous constraint)?
Example:
set_clock_groups -name async_clocks -asynchronous \
-group [get_clocks -include_generated_clocks ext_spi_clk] \
-group [get_clocks -include_generated_clocks axi_clk]

2) Should I keep the core "as is", or should I modify the source code in order to downgrade the warnings? I could, for example:
- add the ASYNC_REG property to flip-flops missing it (answering CDC-2)
- add a flip-flop right before the synchronizer where combinatorial logic is detected (answering CDC-10)

3) What to do about CDC-15 warning, "Clock enable controlled CDC structure detected"?

 

Row  ID      Severity  Description                                         Depth  Exception                Source (From)                                                                                                                                                                                                                 Destination (To)
---  ------  --------  --------------------------------------------------  -----  -----------------------  ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------  ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  1  CDC-2   Warning   1-bit synchronized with missing ASYNC_REG property      2  None                     DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_CDC.SPICR_RX_FIFO_Rst_en_d1_reg/C                                                                                                  DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_CDC.RX_FIFO_RST_AX2S_1/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
 17  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_0_6/RAMA/CLK              DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[0]/D
 18  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_0_6/RAMB/CLK              DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[1]/D
 19  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_0_6/RAMC/CLK              DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[2]/D
 20  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_0_6/RAMD/CLK              DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[3]/D
 21  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_0_6/RAME/CLK              DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[4]/D
 22  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_0_6/RAMF/CLK              DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[5]/D
 23  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_0_6/RAMG/CLK              DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[6]/D
 24  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_7_13/RAMA/CLK             DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[7]/D
 25  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_7_13/RAMB/CLK             DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[8]/D
 26  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_7_13/RAMC/CLK             DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[9]/D
 27  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_7_13/RAMD/CLK             DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[10]/D
 28  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_7_13/RAME/CLK             DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[11]/D
 29  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_7_13/RAMF/CLK             DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[12]/D
 30  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_7_13/RAMG/CLK             DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[13]/D
 31  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_14_14/DP/CLK              DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[14]/D
 32  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_63_15_15/DP/CLK              DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[15]/D
 33  CDC-10  Critical  Combinatorial logic detected before a synchronizer      2  None                     DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/CONTROL_REG_I/CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]/C                                                                                                           DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/PRE
 34  CDC-10  Critical  Combinatorial logic detected before a synchronizer      2  None                     DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I/Bus2IP_Reset_i_reg/C                                                                                                                                                      DUT/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/RESET_SYNC_AX2S_1/D
 35  CDC-1   Critical  1-bit unknown CDC circuitry                             0  None                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg/C                                                                                          QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_1_CDC/D
 36  CDC-2   Warning   1-bit synchronized with missing ASYNC_REG property      2  None                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/CONTROL_REG_I/CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]/C                                                                                                   QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_1_CDC/D
 37  CDC-2   Warning   1-bit synchronized with missing ASYNC_REG property      2  None                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/CONTROL_REG_I/CONTROL_REG_5_9_GENERATE[8].SPICR_data_int_reg[8]/C                                                                                                   QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_1_CDC/D
 38  CDC-2   Warning   1-bit synchronized with missing ASYNC_REG property      2  None                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/CONTROL_REG_I/CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]/C                                                                                                   QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC/D
 39  CDC-2   Warning   1-bit synchronized with missing ASYNC_REG property      2  None                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/CONTROL_REG_I/CONTROL_REG_5_9_GENERATE[6].SPICR_data_int_reg[6]/C                                                                                                   QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_1_CDC/D
 40  CDC-2   Warning   1-bit synchronized with missing ASYNC_REG property      2  None                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/CONTROL_REG_I/CONTROL_REG_5_9_GENERATE[5].SPICR_data_int_reg[5]/C                                                                                                   QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_1_CDC/D
 41  CDC-2   Warning   1-bit synchronized with missing ASYNC_REG property      2  None                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/CONTROL_REG_I/CONTROL_REG_1_2_GENERATE[2].SPICR_data_int_reg[2]/C                                                                                                   QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_1_CDC/D
 42  CDC-2   Warning   1-bit synchronized with missing ASYNC_REG property      2  None                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/CONTROL_REG_I/CONTROL_REG_1_2_GENERATE[1].SPICR_data_int_reg[1]/C                                                                                                   QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_1_CDC/D
 43  CDC-2   Warning   1-bit synchronized with missing ASYNC_REG property      2  None                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/CONTROL_REG_I/SPICR_data_int_reg[0]/C                                                                                                                               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_1_CDC/D
 44  CDC-2   Warning   1-bit synchronized with missing ASYNC_REG property      2  None                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/CONTROL_REG_I/SPICR_REG_78_GENERATE[8].SPI_TRISTATE_CONTROL_I/C                                                                                                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_1_CDC/D
 45  CDC-2   Warning   1-bit synchronized with missing ASYNC_REG property      2  None                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/CONTROL_REG_I/SPICR_REG_78_GENERATE[7].SPI_TRISTATE_CONTROL_I/C                                                                                                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_1_CDC/D
 46  CDC-2   Warning   1-bit synchronized with missing ASYNC_REG property      2  None                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/STATUS_REG_MODE_0_GEN.STATUS_SLAVE_SEL_REG_I/SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]/C                                                                              QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC/D
 47  CDC-2   Warning   1-bit synchronized with missing ASYNC_REG property      2  None                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/STATUS_REG_MODE_0_GEN.STATUS_SLAVE_SEL_REG_I/modf_reg/C                                                                                                             QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SR_3_MODF_AX2S_1_CDC/D
 51  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMA/CLK      QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[0]/D
 52  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMA_D1/CLK   QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[1]/D
 53  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMB/CLK      QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[2]/D
 54  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMB_D1/CLK   QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[3]/D
 55  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMC/CLK      QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[4]/D
 56  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMC_D1/CLK   QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[5]/D
 57  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMD/CLK      QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[6]/D
 58  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMD_D1/CLK   QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[7]/D
 59  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAME/CLK      QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[8]/D
 60  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAME_D1/CLK   QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[9]/D
 61  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMF/CLK      QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[10]/D
 62  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMF_D1/CLK   QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[11]/D
 63  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMG/CLK      QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[12]/D
 64  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMG_D1/CLK   QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[13]/D
 65  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_6_11/RAMA/CLK     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[14]/D
 66  CDC-15  Warning   Clock enable controlled CDC structure detected          0  False Path               QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_6_11/RAMA_D1/CLK  QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[15]/D
 67  CDC-10  Critical  Combinatorial logic detected before a synchronizer      2  None                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/CONTROL_REG_I/CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]/C                                                                                                   QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/PRE
 68  CDC-10  Critical  Combinatorial logic detected before a synchronizer      2  None                     QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I/Bus2IP_Reset_i_reg/C                                                                                                                                              QSPI_MASTER/U0/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/RESET_SYNC_AXI_SPI_CLK_INST/RESET_SYNC_AX2S_1/D

 

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Historian
Historian
20,689 Views
Registered: ‎01-23-2009

Re: CDC analysis (AXI Quad SPI core v 3.2)

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The IP core provides a few xdc files reporting constraints such as set_max_delay and set_false_path. If I declare the clocks as asynchronous, the original Xilinx constraints will be overwritten. Are you sure it is a good idea to overwrite the original Xilinx "set_max_delay" constraint with "set_clock_groups -asynchronous"?

 

As you suspect, it is not a good idea to do the set_clock_groups -asynchronous; these will, indeed, override the correct constraints that exist in the IP, thus underconstraining your clock crossing circuits in the IP.

 

It doesn't look like constraints are the problem here - it looks like the architecture of some of the CDC circuits are not being recognized by the report_cdc command, and that most of them don't have the ASYNC_REG property set on them.

 

The ASYNC_REG property is best set in the RTL code itself, but if this is an IP, they can be set in the XDC files (either for the core, or your own user XDC file). The unknown CDCs should be investigated to see if they are proper or not...

 

The report_cdc command is a relatively new one, and hence there are a couple of possibilities

  - the report_cdc is mis-flagging a non-CDC as an improper CDC

  - the report_cdc is unable to identify a proper CDC

  - the IP has incorrect (or incomplete) CDCs (and/or properties and/or constraints on those CDCs) and they need to be corrected

      - if the QSPI core is a Xilinx core, it is possible that it wasn't run through the report_cdc (which wasn't available on previous versions of the tool) to flag these issues...

 

Avrum

5 Replies
Scholar austin
Scholar
10,942 Views
Registered: ‎02-27-2008

Re: CDC analysis (AXI Quad SPI core v 3.2)

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m,

 

Having one clock (fully synchronous) is best, but often impractical.

 

Placing the paths with the correct clock domiain crossing (CDC) constraints between asynchronous clocks  will allow the tools to properly implement them to reduce the problem of metastability, and remove timing violations.  You may still see warnings just letting you know you have a CDC (warnings are there for you to examine and accept or correct depening on what YOU need).

 

You not only need to declare this path as needing the async register, but the clocks must also be noted as asynchronous (note that Vivado assumes all clocks are asynchronous by default, ISE assumes they are all synchronous).

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor marwise
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Registered: ‎02-26-2016

Re: CDC analysis (AXI Quad SPI core v 3.2)

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Thanks for your reply, Austin.

note that Vivado assumes all clocks are asynchronous by default, ISE assumes they are all synchronous

I believe there is a typo, here, as Xilinx documents state that Vivado assumes that all clocks are synchronous by default, and not the opposite.

The IP core provides a few xdc files reporting constraints such as set_max_delay and set_false_path. If I declare the clocks as asynchronous, the original Xilinx constraints will be overwritten. Are you sure it is a good idea to overwrite the original Xilinx "set_max_delay" constraint with "set_clock_groups -asynchronous"?

 

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Scholar austin
Scholar
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Registered: ‎02-27-2008

Re: CDC analysis (AXI Quad SPI core v 3.2)

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m,

 

My mistake (assumes synchronous vs. asynchronous).

 

Apply the constraint for asynchronous clocks to get a valid timing report.  Apply the asynchronous register constraint to get a proper clock domain crossing pair (or more) of DFF to avoid metastability.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Historian
Historian
20,690 Views
Registered: ‎01-23-2009

Re: CDC analysis (AXI Quad SPI core v 3.2)

Jump to solution

The IP core provides a few xdc files reporting constraints such as set_max_delay and set_false_path. If I declare the clocks as asynchronous, the original Xilinx constraints will be overwritten. Are you sure it is a good idea to overwrite the original Xilinx "set_max_delay" constraint with "set_clock_groups -asynchronous"?

 

As you suspect, it is not a good idea to do the set_clock_groups -asynchronous; these will, indeed, override the correct constraints that exist in the IP, thus underconstraining your clock crossing circuits in the IP.

 

It doesn't look like constraints are the problem here - it looks like the architecture of some of the CDC circuits are not being recognized by the report_cdc command, and that most of them don't have the ASYNC_REG property set on them.

 

The ASYNC_REG property is best set in the RTL code itself, but if this is an IP, they can be set in the XDC files (either for the core, or your own user XDC file). The unknown CDCs should be investigated to see if they are proper or not...

 

The report_cdc command is a relatively new one, and hence there are a couple of possibilities

  - the report_cdc is mis-flagging a non-CDC as an improper CDC

  - the report_cdc is unable to identify a proper CDC

  - the IP has incorrect (or incomplete) CDCs (and/or properties and/or constraints on those CDCs) and they need to be corrected

      - if the QSPI core is a Xilinx core, it is possible that it wasn't run through the report_cdc (which wasn't available on previous versions of the tool) to flag these issues...

 

Avrum

Visitor marwise
Visitor
10,649 Views
Registered: ‎02-26-2016

Re: CDC analysis (AXI Quad SPI core v 3.2)

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Thanks for the help, Avrum

Following your advice, I set the ASYNC_REG property using the xdc files. Now I don't see CDC-10 warning anymore.

As for the missing flip-flops, I added them directly in the visible source code of the IP. CDC-2 critical warning was solved this way.

 

I decided to ignore the CDC-15 warning for the time being, as it is related to a part of code I cannot access.

I hope Xilinx will update the "AXI Quad SPI" core with these fixes in future releases of the core.

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