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Explorer
Explorer
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Registered: ‎07-04-2014

CDC from SPI miso

Hi All,

 

I am re-writting a spi module that had some mistakes in it. Right now, I am coding the SPI master side. I am looking at the miso line.

 

I have the following where sclk_i is the fast clock input of the module. It is then divided by 4 to get the actual spi_sclk_o with which the spi_miso_i is aligned

  always @(posedge sclk_i)
    begin : rx_bit_proc
         if(samp_ce == 1'b1)
             rx_bit_reg <= spi_miso_i;
         end 

 

 

If I write the above to get the data_in values in the sclk_i clock domain. Am I doing it right?

 

sclk_i is aligned with spi_sclk_o  so in theory, I do not need any CDC. Vivado complains and tells me that there is an unknown CDC circuitry because spi_miso_i is in fact an async signal coming from the external world.

 

I have set the input delay like so:

 

set_input_delay -clock [get_clocks ADC_SCLK] -min -add_delay 0.000 [get_ports ADC_MISO_I[*]]
set_input_delay -clock [get_clocks ADC_SCLK] -max -add_delay 81.500 [get_ports ADC_MISO_I[*]]

see http://www.analog.com/media/en/technical-documentation/data-sheets/AD7734.pdf  at page 6 

 

where I added 1.5ns to account for cable delays.

 

 

Maybe Vivado has got a point! Maybe I should be adding some CDC there because I may get spi_miso_i  which is not perfectly aligned because of different pcb delay or small change in cable length. What do you think?

 

 

 

Another thing... in the original file version the sensitivity list contained spi_miso_i and vivado was quiet about cdc.

rx_bit_proc : process (sclk_i, spi_miso_i) is
    begin
        if sclk_i'event and sclk_i = '1' then
            if samp_ce = '1' then
                rx_bit_reg <= spi_miso_i;
            end if;
        end if;
    end process rx_bit_proc;

 

 

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