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Explorer
Explorer
1,624 Views
Registered: ‎05-14-2015

CDC timing constraint

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If a design is like below, can somebody help to check if my timing constraint is correct and good enough? 

1.  It contains CLK_A, CLK_B, CLK_C and CLK_D

2.  A high speed video data stream is crossing CLK_A and CLK_B domain.  The CDC circuit between CLK_A and CLK_B is using Xilinx's XPM module "XPM_MEMORY_SDPRAM". It's a simple dual port RAM. This RAM is used to form a FIFO to act as CDC circuit from CLK_A to CLK_B. 

3. Between CLK_A and CLK_C, there is no high speed video data stream. There is only some low speed, low transition frequency  signals which are transferred between these 2 clock domains.  2 back-to-back Flip-Flops have been used as CDC circuit to transfer these data between these 2 clock domains. 

4. Between CLK_A and CLK_D, there are both high speed video stream and low-speed and low-transition-frequency signals. "XPM_MEMORY_SDPRAM" has been used for video stream from CLK_A to CLK_D.  2 back-to-back Flip-Flops have been used as CDC circuit for  low-speed and low-transition-frequency signals.

5.  CLK_B, CLK_C and CLK_D are completely unrelated. There are no paths in-between any of pairs of them. 

5.  CLK_A=150MHZ.  CLK_B=300MHZ, CLK_C=100MHZ; CLK_D=297MHZ;

 

In order to constrain them properly, the following constraints will be implemented: 

set period_CLK_B [expr ([get_property PERIOD [get_clocks CLK_B]]-0.1)] 
set period_CLK_D [expr ([get_property PERIOD [get_clocks CLK_D]]-0.1)]

;# CDC between CLK_A and CLK_B
set_max_delay $period_CLK_B -datapath_only -from [get_clocks CLK_A] -to [get_clocks CLK_B]

;# CDC between CLK_A and CLK_C
set_clock_groups -asynchronous -group [get_clocks CLK_A] -group [get_clocks CLK_C]

;# CDC between CLK_A and CLK_D
set_max_delay $period_CLK_D -datapath_only -from [get_clocks CLK_A] -to [get_clocks CLK_D]
set_max_delay $period_CLK_D -datapath_only -from [get_clocks CLK_D] -to [get_clocks CLK_A]

Do you think these constraints are correct? Is it over-constrainted because I always use the period of the fastest clock as the value of max_delay? 

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Historian
Historian
2,281 Views
Registered: ‎01-23-2009

Re: CDC timing constraint

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My only concern is your statement that you are using the XPM_MEMORY_SDPRAM as the clock crossing mechanism.

 

A dual port memory with asynchronous clocks can form part of a clock domain crossing circuit, but it needs other stuff around it. A dual port RAM is only a clock crossing circuit if you guarantee that there is "enough" separation between a write to a given address location and the read from that same address location on the other port. To make sure that this is the case, there must be some "other" communication between the clock domains.

 

The most common mechanism of making sure you don't access the same location on both sides near the same time is to use the RAM as a FIFO (which is what you say you are using). The empty and full generation mechanisms are what guarantees that the read and write side don't access the same location at the same time. So the RAM doesn't actually place any requirements in terms of CDC constraints, but the empty/full generation requires some serious consideration as to how the clock domain crossing is done, and these CDC circuits do require constraints.

 

That being said, most CDC circuits are properly constrained by a set_max_delay -datapath_only with the smaller of the two periods (although that may technically overconstrain one side of the CDC).

 

Rather than using the XPM_MEMORY_SDPRAM, why not use the built in FIFO in the FIFO36/FIFO18? If you want a FIFO in distributed memory (rather than block memory - i.e. a smaller FIFO), why not use the FIFO generator (or are you trying to avoid IP)? The advantage to these is that they come fully constrained...

 

Avrum

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Xilinx Employee
Xilinx Employee
1,589 Views
Registered: ‎05-06-2008

Re: CDC timing constraint

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Hello softwind555,

 

I recommend using the set_max_delay between CLKA and CLKC.  A timing requirement between these clock domains will drive better placement.  

 

I think the rest of the cross clock domain constraints are fine.

 

Thanks,

Chris

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Historian
Historian
2,282 Views
Registered: ‎01-23-2009

Re: CDC timing constraint

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My only concern is your statement that you are using the XPM_MEMORY_SDPRAM as the clock crossing mechanism.

 

A dual port memory with asynchronous clocks can form part of a clock domain crossing circuit, but it needs other stuff around it. A dual port RAM is only a clock crossing circuit if you guarantee that there is "enough" separation between a write to a given address location and the read from that same address location on the other port. To make sure that this is the case, there must be some "other" communication between the clock domains.

 

The most common mechanism of making sure you don't access the same location on both sides near the same time is to use the RAM as a FIFO (which is what you say you are using). The empty and full generation mechanisms are what guarantees that the read and write side don't access the same location at the same time. So the RAM doesn't actually place any requirements in terms of CDC constraints, but the empty/full generation requires some serious consideration as to how the clock domain crossing is done, and these CDC circuits do require constraints.

 

That being said, most CDC circuits are properly constrained by a set_max_delay -datapath_only with the smaller of the two periods (although that may technically overconstrain one side of the CDC).

 

Rather than using the XPM_MEMORY_SDPRAM, why not use the built in FIFO in the FIFO36/FIFO18? If you want a FIFO in distributed memory (rather than block memory - i.e. a smaller FIFO), why not use the FIFO generator (or are you trying to avoid IP)? The advantage to these is that they come fully constrained...

 

Avrum

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Explorer
Explorer
1,570 Views
Registered: ‎05-14-2015

Re: CDC timing constraint

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@avrumw, Thank you for your detailed explanation. 

 

Indeed, we have mechanism to make sure the write and read will not access the same location at the same time. 

The reason why I use "XPM_MEMORY_SDPRAM" is because it has a "MEMORY_PRIMITIVE" attribute and I can set it to "auto", so VIVADO will automatically select "distributed", "block" or "ultra"  RAM for "XPM_MEMORY_SDPRAM". Another reason is exactly as you mentioned, to avoid IP. 

 

In page 70 of UG974(V2017.2

)(Introduction on XPM_MEMORY_SDPRAM), the following words are mentioned: 

dualport.png

I don't really understand what the recommended constraint is doing. Can you help to explain a little? 

 

I'm not familiar with FIFO36/18. What's the advantage of this? Does it need any CDC constraint?

 

 

 

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Historian
Historian
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Registered: ‎01-23-2009

Re: CDC timing constraint

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I'm not familiar with FIFO36/18. What's the advantage of this? Does it need any CDC constraint?

 

Each block RAM in the FPGA can be either a 36kb block RAM, two 18kb block RAMs, one 36kb FIFO or one 18kb FIFO and one 18kb block RAM.

 

When configured as a FIFO (FIFO18 or FIFO36) the block RAM uses dedicated built-in address and flag generation mechanisms to implement the FIFO in the block RAM. This FIFO logic is built inside the block RAM hard block, and hence is not part of the FPGA fabric logic. This means:

  - it comes for free

  - it is very highly tested under pretty much all conditions and

  - it doesn't need any CDC constraints (all paths between the clock domains are completely inside the hard block, are timing correct by design, and are not seen by the timing engine, hence requiring no constraints).

 

The FIFO36/18 has lots of functions and options, including first-word-fall-through mode, programmable almost full and almost empty, support for different clock latencies (for high speed operation), different widths... If you need a big FIFO, these are the way to go...

 

These are fully described in Memory Resources User Guide (i.e. UG473 for the 7-series); there is a complete section describing the Built-In FIFO Support.

 

Avrum

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