12-17-2016 04:21 AM
I am working on zynq7020 customized board.
I need to make my design confidence level to HIGH. now it is LOW.
For that I referred the UG997. I followed the steps they have mentioned there after that still design confidence level is low.. but in tcl console I am getting "Design nets matched = 8 of 22083" this message .
how can I meet this condition .. please someone help me
12-17-2016 08:52 PM
Are you generating saif with post implementation functional simulation?
When you click on the Low in "Confidence Level: Low" you will know whether it is due to IO Activity/Clock Activity/Design State etc..