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theertharamesha
Adventurer
Adventurer
5,238 Views
Registered: ‎08-21-2016

CONFIDENCE LEVEL

HI ALL,

I am working on zynq7020 customized board.

 

  I need to make my design confidence level to HIGH. now  it is LOW.

For that I referred the UG997. I followed the steps they have mentioned there after that still design confidence level is low..  but in tcl console I am getting "Design nets matched = 8 of 22083" this message .

 

how can I meet this condition .. please someone help me

 

 

with regards

ramesh

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5 Replies
austin
Scholar
Scholar
5,222 Views
Registered: ‎02-27-2008

Are you using the version of software listed in the UG?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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svanapar
Explorer
Explorer
5,195 Views
Registered: ‎11-25-2015

@theertharamesha

 

Are you generating saif with post implementation functional simulation?

When you click on the Low in "Confidence Level: Low" you will know whether it is due to IO Activity/Clock Activity/Design State etc..

 

Regards,

Sravanthi

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theertharamesha
Adventurer
Adventurer
5,167 Views
Registered: ‎08-21-2016

Thank for the reply Austin,

 

ya, I am using the same version of software what they have explained in the UG

 

 

 

REGARDS

RAMESH

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svanapar
Explorer
Explorer
5,078 Views
Registered: ‎11-25-2015

@theertharamesha

 

Is your query addressed?

 

Regards,

Sravanthi

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theertharamesha
Adventurer
Adventurer
3,427 Views
Registered: ‎08-21-2016

@svanapar

 

no not yet I am cleared

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