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Visitor
Visitor
9,579 Views
Registered: ‎01-13-2009

CPLD Timing Problem/Question

I am using an XC2C256-7 cpld and am trying to set a constraint for a data bus. I am using ISE 10.1.03. The read data bus is a transparent latch done with the following equations

 

process(LIME_D, lime_xrd_int)
begin
 if(lime_xrd_int = '0') then --  transparent latch data
  lime_d_int <= LIME_D;
 end if;
end process;

CPU_D <= lime_d_int when cpu_oe_int = '0' else (others => 'Z');

 

Everthing seems to work fine but I am trying to set the constraint for the pad to pad delay for LIME_D to CPU_D. I place the following constraint in my UCF file:

 

NET cpu_d(*) TNM_NET = CPU_DATA;
NET lime_d(*) TNM_NET = LIME_DATA;
TIMESPEC TS_lime_to_cpu_data=FROM LIME_DATA TO CPU_DATA 11.3 ns;

 

When I implement my top module (which does the timing analysis as part of the process) I get the following warning:

 

WARNING:Cpld:310 - Cannot apply TIMESPEC TS_lime_to_cpu_data =
   FROM:LIME_DATA:TO:CPU_DATA:11.300nS because of one of the following: (a) a
   signal name was not found; (b) a signal was removed or renamed due to
   optimization; (c) there is no path between the FROM node and TO node in the
   TIMESPEC.

 

The timing report shows 0 paths that this applies to but further down the report I see the following:

 

Source PadDestination PadDelay

LIME_D<0>CPU_D<0>5.100
LIME_D<10>CPU_D<10>5.100
LIME_D<11>CPU_D<11>5.100
LIME_D<12>CPU_D<12>5.100
LIME_D<13>CPU_D<13>5.100
LIME_D<14>CPU_D<14>5.100
LIME_D<15>CPU_D<15>5.100
LIME_D<1>CPU_D<1>5.100
LIME_D<2>CPU_D<2>5.100
LIME_D<3>CPU_D<3>5.100
LIME_D<4>CPU_D<4>5.100
LIME_D<5>CPU_D<5>5.100
LIME_D<6>CPU_D<6>5.100
LIME_D<7>CPU_D<7>5.100
LIME_D<8>CPU_D<8>5.100
LIME_D<9>CPU_D<9>5.100


 So is the delay 5.1 nS? What am I doing wrong?

 

 

thanks

 

Mike 

 

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Xilinx Employee
Xilinx Employee
9,554 Views
Registered: ‎08-13-2007

Re: CPLD Timing Problem/Question

I would try this again using the same bus delimiter in your constraints as your code (e.g. braces instead of parenthesis)

 

bt

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Visitor
Visitor
9,551 Views
Registered: ‎01-13-2009

Re: CPLD Timing Problem/Question

I tried that but the result was the same.

 

thanks

 

Mike

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Xilinx Employee
Xilinx Employee
9,546 Views
Registered: ‎08-13-2007

Re: CPLD Timing Problem/Question

I think you should be using TNM instead of TNM_NET.

 

If that doesn't work - try this:

 

TIMESPEC TS_P2P=FROM PADS TO PADS 11.3;

 

bt

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Visitor
Visitor
9,537 Views
Registered: ‎01-13-2009

Re: CPLD Timing Problem/Question

TNM did not solve the problem.

 

TIMESPEC TS_P2P=FROM PADS TO PADS 11.3;

 

Caused 64 new violation unrelated to the one I am trying measure (and ones I do not care about). I have a number of clock pad to output pad that violate this. It is nice to learn a new command though.

 

thanks

 

Mike

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Xilinx Employee
Xilinx Employee
9,534 Views
Registered: ‎08-13-2007

Re: CPLD Timing Problem/Question

When you tried TNM, did you use the bus limiter (braces) listed in your timing report?

 

bt

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