01-26-2009 01:51 PM
I am using an XC2C256-7 cpld and am trying to set a constraint for a data bus. I am using ISE 10.1.03. The read data bus is a transparent latch done with the following equations
if(lime_xrd_int = '0') then -- transparent latch data
lime_d_int <= LIME_D;
CPU_D <= lime_d_int when cpu_oe_int = '0' else (others => 'Z');
Everthing seems to work fine but I am trying to set the constraint for the pad to pad delay for LIME_D to CPU_D. I place the following constraint in my UCF file:
NET cpu_d(*) TNM_NET = CPU_DATA;
NET lime_d(*) TNM_NET = LIME_DATA;
TIMESPEC TS_lime_to_cpu_data=FROM LIME_DATA TO CPU_DATA 11.3 ns;
When I implement my top module (which does the timing analysis as part of the process) I get the following warning:
WARNING:Cpld:310 - Cannot apply TIMESPEC TS_lime_to_cpu_data =
FROM:LIME_DATA:TO:CPU_DATA:11.300nS because of one of the following: (a) a
signal name was not found; (b) a signal was removed or renamed due to
optimization; (c) there is no path between the FROM node and TO node in the
The timing report shows 0 paths that this applies to but further down the report I see the following:
|Source Pad||Destination Pad||Delay|
So is the delay 5.1 nS? What am I doing wrong?
01-30-2009 08:11 AM
TNM did not solve the problem.
TIMESPEC TS_P2P=FROM PADS TO PADS 11.3;
Caused 64 new violation unrelated to the one I am trying measure (and ones I do not care about). I have a number of clock pad to output pad that violate this. It is nice to learn a new command though.