10-11-2017 09:14 PM
virtex 6 , ISE14.7
clocks topology is as following:
ckin1(pad)->ibuf->bufr(clk1)->bufg->clk1bufg ---> logic1
=>bufgmux->clk3 ---> logic3
ckin2(pad)->MMCM-> clk2 ->bufg->clk2bufg ---> logic2
~ clk1 is 112Mhz and clk2 is 27Mhz;
~ clk1 drive I0 of bufgmux; clk2 drive I1 of bufgmux;
~ there are paths between logic1 and logic3; there are also paths between logic2 and logic3;
here comes the constrain I set in UCF:
. period with priority 1 for clk1;
. period with priority 2 for clk2(I don't set period constrain on ckin2);
~ these are used to propagate period constrain of clk1 to clk3;
. PIN bufgmux.I1 TIG
~ according to ug612, this is used for clock skew check for clk3;
. set paths between clk1 and clk2 as false
1. Can ISE guarantee the clock balance between clk1 and clk3 with these constrains?
the paths between logic1 and logic3 should be timed.
Although Timing report says there is no violation, but the function doesn't work well all the time. I can not get constant right result after each map and P&R in ISE . I try SmartExplore, even when there's no timing violation under different strategies, some results are right and some are not.
It seems there is some timging issue, I am not sure it is because of my constrain or ISE tool?
How can I make clock balance when using bufgmux in ISE ?
Are the paths between logic1 and logic3 really be timed with these constrains?
2. I want to check the timing for a path from logic1 to logic3 to find out if it is covered by my constrain or not, I set the start point FF and end point FF in planhead, but it reports that "timing result is empty". How do I analyse a single path I want in ISE?
3. what is the priority of clk3? Can the priority constrain be propagated to clk3? When I have cascaded bufgmux (for ASIC prototyping), Do I need set priority for clk3 when it drive the input of another bufgmux?
4. Does ISE generate a new constrain for clk3? Does ISE treat clk3 as a different clock against clk1?
5. I didn't define timing group for clk3, does ISE create timing group for it?
From the timing report(twx), I can see paths between logic3 and logic1 listed under the TIG constrain of paths between clk1 and clk2. Seems that paths between logic3 and logic1 also be ignored. why? Does the timing group for clk2 cover the logic3?
10-12-2017 12:04 PM
Here are some answers (but not all):
a BUFG and a BUFGMUX are really the same resource. So the clk1bufg and the clk3 are both going through one BUFG/BUFGMUX to a different global clock network. All global clock lines are balanced, and hence the skew between these clocks at the endpoints will be "small" - more than the skew on one clock network, but not by much.
So clock skew isn't your problem.
That being said, constraining things like this are really difficult in ISE. I am pretty sure it can't be done "right" - so that the paths between logic1<->logic3 are timed at 112MHz and the paths between logic2 <-> logic3 are timed at 27MHz.
Also, it has been a LOOONG time since I have tried to do this in ISE, so I don't think I remember the details of what you can and can't do.
In ISE you cannot ask the tools to report on a specific paths against your constraints - its simply not possible - so it is very hard to figure out exactly how ISE has interpreted your constraints.
You also can't time the same design "twice" - once at one frequency and once at another - since the constraints are read in to the design by ngdbuild - before place and route...
I am not certain what PlanAhead can do for you... PlanAhead is really somewhere between Vivado and ISE, so when you ask it to "report_timing" it is using the Vivado timing engine using annotations from trce; how it handles constraints is not necessarily the same as how (say) map and par handle the same constraints. The only way to get "real" timing information out of ISE (even using PlanAhead) is to use timingan, and it has very primitive capabilities.
As for the rest - I just don't remember. It has been years since I have really worked with ISE, and I have forgotten the subtleties (or idiosyncrasies) of this stuff...
Any chance you can change devices (like a Kintex-7) and work with Vivado instead? This stuff is fully supported in Vivado...
10-27-2017 06:16 AM
Thanks @avrumw , sorry for the late reply. I am still working on digging this problem these days, thanks for your hints. I removed the TIG constraint between clk1 and clk2. ISE has its rules to constrain the clocks to BUFGMUX, it is not what I thought before.
In ISE, it seems that the path between logic1 and logic3 is timed at 112Mhz, and path from logic2 to logic3 is timed at 27Mhz. For path from logic3 to logic2, it treat it as a cross clock domain path(start at clk1 and end at clk2). The TIG constraint for path between clk1and clk3 will make the path from logic2 to logic3 to be falsed.
Athough I don't understand it quite clear yet, I tried to make things easier by removing BUFGMUX temporarily.
Our FPGA platform is developed years ago, maybe next project we will move to 7 series.