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527 Views
Registered: ‎01-30-2014

Can not find the valid clock object for set_clock_groups -asynchronous

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Here is my timing error from crossing a clock domain.  The registers crossing the domain here are a grey code counter designed to cross clock domains safely. 

 

Name

Slack

Levels

High Fanout

From

To

Total Delay

Logic Delay

Net Delay

Requirement

Source Clock

Destination Clock

Exception

Clock Uncertainty

Path 169

-2.78

0

1

instSenDecode1/instPixelFifo1/wrCntGry_w_reg[3]/C

instSenDecode1/instPixelFifo1/wrCntGry_r_reg[3]/D

5.86

0.40

5.46

0.80

senSdClk

clkout0

 

0.19

Path 170

-2.33

0

1

instSenDecode0/instPixelFifo1/wrCntGry_w_reg[8]/C

instSenDecode0/instPixelFifo1/wrCntGry_r_reg[8]/D

5.36

0.40

4.96

0.80

senSdClk

clkout0

 

0.19

Path 171

-2.11

0

1

instSenDecode1/instPixelFifo1/wrCntGry_w_reg[4]/C

instSenDecode1/instPixelFifo1/wrCntGry_r_reg[4]/D

5.17

0.40

4.77

0.80

senSdClk

clkout0

 

0.19

Path 172

-2.00

0

1

instSenDecode0/instPixelFifo1/wrCntGry_w_reg[6]/C

instSenDecode0/instPixelFifo1/wrCntGry_r_reg[6]/D

5.21

0.43

4.77

0.80

senSdClk

clkout0

 

0.19

Path 173

-2.00

0

1

instSenDecode1/instPixelFifo1/wrCntGry_w_reg[5]/C

instSenDecode1/instPixelFifo1/wrCntGry_r_reg[5]/D

5.22

0.43

4.79

0.80

senSdClk

clkout0

 

0.19

Path 174

-1.93

0

1

instSenDecode0/instPixelFifo1/wrCntGry_w_reg[5]/C

instSenDecode0/instPixelFifo1/wrCntGry_r_reg[5]/D

5.10

0.38

4.72

0.80

senSdClk

clkout0

 

0.19

Path 175

-1.90

1

1

instSenDecode1/SoF_reg/C

instStreamMux0/OSoF_reg/D

5.16

0.48

4.67

0.80

senSdClk

clkout0

 

0.19

Path 176

-1.84

0

1

instSenDecode1/instPixelFifo1/wrCntGry_w_reg[8]/C

instSenDecode1/instPixelFifo1/wrCntGry_r_reg[8]/D

4.87

0.40

4.48

0.80

senSdClk

clkout0

 

0.19

Path 177

-1.78

0

1

instSenDecode1/instPixelFifo1/wrCntGry_w_reg[9]/C

instSenDecode1/instPixelFifo1/wrCntGry_r_reg[9]/D

4.97

0.38

4.59

0.80

senSdClk

clkout0

 

0.19

Path 178

-1.73

0

1

instSenDecode0/instPixelFifo1/wrCntGry_w_reg[2]/C

instSenDecode0/instPixelFifo1/wrCntGry_r_reg[2]/D

4.76

0.35

4.41

0.80

senSdClk

clkout0

 

0.19

 

To eliminate this timing analysis I would like to use set_clock_groups -asynchronous.  These two clocks have no relationship in operation.  This is my best attempt at the proper syntax (line 367):

set_clock_groups -asynchronous -group [get_clocks senSdClk] -group [get_clocks clkout0]

When I synthesise and implement I get these critical warnings:

Synthesis
synth_1
[Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks clk25_SystemClks -include_generated_clocks]'. ["/media/psf/FPGA/Falcon/Falcon.srcs/constrs_1/new/Falcon.xdc":365]

[Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks senSdClk]'. ["/media/psf/FPGA/Falcon/Falcon.srcs/constrs_1/new/Falcon.xdc":367]

[Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks clkout0]'. ["/media/psf/FPGA/Falcon/Falcon.srcs/constrs_1/new/Falcon.xdc":367]

Implementation
Design Initialization
[Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks senSdClk]'. ["/media/psf/FPGA/Falcon/Falcon.srcs/constrs_1/new/Falcon.xdc":367]

[Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks clkout0]'. ["/media/psf/FPGA/Falcon/Falcon.srcs/constrs_1/new/Falcon.xdc":367]

[Constraints 18-4644] set_clock_groups: All clock groups specified are empty. Please specify atleast one clock group which is not empty. ["/media/psf/FPGA/Falcon/Falcon.srcs/constrs_1/new/Falcon.xdc":367]

Route Design
[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

Here are the results of report_clocks ang get_clocks recommended to isolate the proper clock name:

report_clocks
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (lin64) Build 2405991 Thu Dec  6 23:36:41 MST 2018
| Date         : Thu Jun 20 09:52:15 2019
| Host         : barry-Parallels-Virtual-Platform running 64-bit Ubuntu 16.04.6 LTS
| Command      : report_clocks
| Design       : Falcon_Top
| Device       : 7a50t-fgg484
| Speed File   : -2  PRODUCTION 1.23 2018-06-13
------------------------------------------------------------------------------------

Clock Report


Attributes
  P: Propagated
  G: Generated
  A: Auto-derived
  R: Renamed
  V: Virtual
  I: Inverted
  S: Pin phase-shifted with Latency mode

Clock                                                                                       Period(ns)  Waveform(ns)    Attributes  Sources
ClkGen6P                                                                                    8.000       {0.000 4.000}   P           {ClkGen6P}
clkfbout_SystemClks                                                                         8.000       {0.000 4.000}   P,G,A       {instSystemClks/inst/mmcm_adv_inst/CLKFBOUT}
clk125_SystemClks                                                                           8.000       {0.000 4.000}   P,G,A       {instSystemClks/inst/mmcm_adv_inst/CLKOUT0}
clk25_SystemClks                                                                            40.000      {0.000 20.000}  P,G,A       {instSystemClks/inst/mmcm_adv_inst/CLKOUT1}
clk125                                                                                      8.000       {0.000 4.000}   P,G,A       {instSystemClks/inst/clkout1_buf/O}
SensClkP                                                                                    16.667      {0.000 8.334}   P           {SensClkP}
intClk65                                                                                    14.286      {0.000 7.143}   P           {instStartup/CFGMCLK}
cxpClk                                                                                      8.000       {0.000 4.000}   P           {instCxpSerDes/U0/CxpTx_init_i/CxpTx_i/gt0_CxpTx_i/gtpe2_i/TXOUTCLK}
cxpRefClk                                                                                   8.000       {0.000 4.000}   P           {instCxpSerDes/U0/CxpTx_init_i/CxpTx_i/gt0_CxpTx_i/gtpe2_i/TXOUTCLKFABRIC}
senSdRefClk                                                                                 6.250       {0.000 3.125}   P           {instCxpSerDes/U0/CxpTx_init_i/CxpTx_i/gt2_CxpTx_i/gtpe2_i/RXOUTCLKFABRIC}
senSdClk                                                                                    20.000      {0.000 10.000}  P           {instCxpSerDes/U0/CxpTx_init_i/CxpTx_i/gt2_CxpTx_i/gtpe2_i/RXOUTCLK}
SerDRefClk0P                                                                                8.000       {0.000 4.000}   P           {SerDRefClk0P}
SerDRefClk1P                                                                                6.250       {0.000 3.125}   P           {SerDRefClk1P}
clkfbout                                                                                    8.000       {0.000 4.000}   P,G,A       {instCxpSerDes/U0/gt_usrclk_source/txoutclk_mmcm0_i/mmcm_adv_inst/CLKFBOUT}
clkout0                                                                                     6.400       {0.000 3.200}   P,G,A       {instCxpSerDes/U0/gt_usrclk_source/txoutclk_mmcm0_i/mmcm_adv_inst/CLKOUT0}
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK  33.000      {0.000 16.500}  P           {dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK}


====================================================
Generated Clocks
====================================================

Generated Clock     : clkfbout_SystemClks
Master Source       : instSystemClks/inst/mmcm_adv_inst/CLKIN1
Master Clock        : ClkGen6P
Multiply By         : 1
Generated Sources   : {instSystemClks/inst/mmcm_adv_inst/CLKFBOUT}

Generated Clock     : clk125_SystemClks
Master Source       : instSystemClks/inst/mmcm_adv_inst/CLKIN1
Master Clock        : ClkGen6P
Multiply By         : 1
Generated Sources   : {instSystemClks/inst/mmcm_adv_inst/CLKOUT0}

Generated Clock     : clk25_SystemClks
Master Source       : instSystemClks/inst/mmcm_adv_inst/CLKIN1
Master Clock        : ClkGen6P
Edges               : {1 2 3}
Edge Shifts(ns)     : {0.000 16.000 32.000}
Generated Sources   : {instSystemClks/inst/mmcm_adv_inst/CLKOUT1}

Generated Clock     : clk125
Master Source       : instSystemClks/inst/clkout1_buf/I
Master Clock        : clk125_SystemClks
Divide By           : 1
Generated Sources   : {instSystemClks/inst/clkout1_buf/O}

Generated Clock     : clkfbout
Master Source       : instCxpSerDes/U0/gt_usrclk_source/txoutclk_mmcm0_i/mmcm_adv_inst/CLKIN1
Master Clock        : cxpClk
Multiply By         : 1
Generated Sources   : {instCxpSerDes/U0/gt_usrclk_source/txoutclk_mmcm0_i/mmcm_adv_inst/CLKFBOUT}

Generated Clock     : clkout0
Master Source       : instCxpSerDes/U0/gt_usrclk_source/txoutclk_mmcm0_i/mmcm_adv_inst/CLKIN1
Master Clock        : cxpClk
Edges               : {1 2 3}
Edge Shifts(ns)     : {0.000 -0.800 -1.600}
Generated Sources   : {instCxpSerDes/U0/gt_usrclk_source/txoutclk_mmcm0_i/mmcm_adv_inst/CLKOUT0}
get_clocks
ClkGen6P clkfbout_SystemClks clk125_SystemClks clk25_SystemClks clk125 SensClkP intClk65 cxpClk cxpRefClk senSdRefClk senSdClk SerDRefClk0P SerDRefClk1P clkfbout clkout0 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK

Clearly I am missing some detail.  Thanks for looking at my issue.

 

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1 Solution

Accepted Solutions
Moderator
Moderator
509 Views
Registered: ‎01-16-2013

Re: Can not find the valid clock object for set_clock_groups -asynchronous

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Hi,

From report_clocks and get_clocks command the results look promising.

I have one suggestion:

Open implemnted design

enter the  set_clock_group command in TCL console and enter

See if it shows same issue? If yes, Is it possible to share test case to debug further?

If No (there is no issue) then follow below suggestions:

How many XDC do you have?

If multiple XDC which XDC is getting parsed before the XDC in which you have exceptions?

Or if its single XDC did you put the exception constraint later after defining clock defination?

For me this looks like constraint parsing order issue than syntax issue.

Thanks,
Yash

 

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5 Replies
Contributor
Contributor
525 Views
Registered: ‎03-29-2016

Re: Can not find the valid clock object for set_clock_groups -asynchronous

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Try,

set_clock_groups -asynchronous -group senSdClk -group clkout0

This is how I use that command. 

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515 Views
Registered: ‎01-30-2014

Re: Can not find the valid clock object for set_clock_groups -asynchronous

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Thank you for taking the time to respond.  I changed the constraint to your suggestion, but the result is the same.

I also tried -group {senSdClk}, synthesis and implementation still cannot find either of those clocks.

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Moderator
Moderator
510 Views
Registered: ‎01-16-2013

Re: Can not find the valid clock object for set_clock_groups -asynchronous

Jump to solution

Hi,

From report_clocks and get_clocks command the results look promising.

I have one suggestion:

Open implemnted design

enter the  set_clock_group command in TCL console and enter

See if it shows same issue? If yes, Is it possible to share test case to debug further?

If No (there is no issue) then follow below suggestions:

How many XDC do you have?

If multiple XDC which XDC is getting parsed before the XDC in which you have exceptions?

Or if its single XDC did you put the exception constraint later after defining clock defination?

For me this looks like constraint parsing order issue than syntax issue.

Thanks,
Yash

 

View solution in original post

Guide avrumw
Guide
485 Views
Registered: ‎01-23-2009

Re: Can not find the valid clock object for set_clock_groups -asynchronous

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First, a word of warning - declaring the paths between the domains on a Gray code clock crosser is not safe. Take a look at this post on why it is not safe to declare Gray code clock crossing paths false.

As for the problems, it looks like you have a constraint order problem. SDC/XDC constraints are Tcl commands - they are executed. This is different than (say) UCF which are files that are parsed - in UCF, order (mostly) doesn't matter, but in XDC it does.

Since the clocks you are trying to use in your set_clock_groups command do appear in the report_clock command, the problem is most likely order - at the time the set_clock_groups command is executed, the clock do not yet exist. Obviously if these commands are in the same XDC file (the command that creates the clock and the set_clock_groups command) then the clock creation must come first. If they are in different files, then you need to manage the constraint file order - make sure that the one that defines the clocks comes before the one that has the set_clock_groups.

Things get even more complicated when some of the constraints come from XDC files associated with IP. By default IP blocks are synthesized "out-of-context" - in a separate synthesis run. During the "top level synthesis" these IP blocks are black boxes - as such any constraints associated with the IP is not read in during the top level synthesis. This is often the cause of problems like this, where the object exists in the opened design, but doesn't exist during synthesis - take a look at this post on how constraints associated with IP are processed.

However, this only explains problems during synthesis, not during implementation. During implementation the IP (and its associated constraints) are read in, so this problem doesn't exist in impementation. Since you are also getting errors during implementation, it must be a file order issue - the XDC file containing the create_clocks is being processed after the XDC file with the set_clock_groups. You can manage this by changing the PROCESSING_ORDER property of the constraints - this can be set to EARLY, NORMAL or LATE - probably changing the one with the set_clock_groups to LATE will fix the problem, but you should probably look at the complete set of constraints and how they are processed - you can see this with the command "report_compile_order -constraints".

Finally a word of caution about "clkout0". This is an auto-generated clock name, and as such probably shouldn't be trusted; for example if you add another MMCM to the system (anywhere else) the name of this clock might change - if you have two MMCMs, the default names for the first one are clkout0 and clkout1, whereas the second one gets clkout0_0 and clkout1_0 - there is no way to tell in advance which is going to be which. So in these cases, I recommend that you refer to the clock by its connectivity, rather than its name. Instead of doing -clock clkout0 (or really -clock [get_clocks clkout0]), you should use something like

[get_clocks -of_objects [get_pins <output_pin_of_clocking_wizard_or_MMCM>]]

This way you are sure you are getting the correct clock.

Avrum

469 Views
Registered: ‎01-30-2014

Re: Can not find the valid clock object for set_clock_groups -asynchronous

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As both your responses predicted, it was an ordering issue. I moved those lines to the bottom of the XDC and the errors are gone. Thanks again for the help.
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