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Visitor boffin
Visitor
10,894 Views
Registered: ‎01-06-2013

Can you use any arbitrary signal in a design as a clock for a submodule ?

I have an emulation project where I have a DUT that is meant to operate at 'x' Mhz (10 Mhz). There is a wrapper around this DUT which is feeding/collecting data at '2x' Mhz (20 Mhz).

 

I want to have the ability to start and stop clock ticks to the DUT, (this is a requirement). So I am generating the clock signal for the DUT using an FSM. When I feed this clock directly to the DUT I run into timing issues.

 

Is there something I need to do to this generated user signal to make it a "clock signal" ?

Please advice.

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Mentor hgleamon1
Mentor
10,888 Views
Registered: ‎11-14-2011

Re: Can you use any arbitrary signal in a design as a clock for a submodule ?

It would be better if you wish to maintain a known relationship between the two clocks to use a single clock domain, routed on the global network, and control the submodule by using your FSM generated signal as a clock enable.

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"That which we must learn to do, we learn by doing." - Aristotle
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Teacher muzaffer
Teacher
10,885 Views
Registered: ‎03-31-2012

Re: Can you use any arbitrary signal in a design as a clock for a submodule ?

If you are not able to modify the DUT to use the original clock and stop signal as a clock enable, your best second option is to make sure that the clock you are generating comes directly from a register the output of which is connected to a global clock buffer. You also need to add a generated clock constraint on the registers output for timing engine to enforce.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Instructor
Instructor
10,878 Views
Registered: ‎08-14-2007

Re: Can you use any arbitrary signal in a design as a clock for a submodule ?

You didn't say what FPGA family you're using.  In the newer ones, you can instantiate a BUFGCE for cleanly gated clocks.

-- Gabor
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Visitor boffin
Visitor
10,876 Views
Registered: ‎01-06-2013

Re: Can you use any arbitrary signal in a design as a clock for a submodule ?

Thanks all for your replies.

I am using Virtex 6 - 760 LX part.

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Instructor
Instructor
10,857 Views
Registered: ‎08-14-2007

Re: Can you use any arbitrary signal in a design as a clock for a submodule ?

The Libraries guide for V6 describes the BUFGCE and BUFGCE_1 macros.  It's usually possible to have a DCM output connect to more than one clock buffer component with high-speed dedicated routing.  So for example your 10 MHz clock from a DCM could drive a BUFG for the constant clock as well as a BUFGCE for the clock to the DUT.  The CE input of the BUFGCE would come from the output of a flip-flop clocked by the straight BUFG.  In order to have low skew between the gated and non-gated clocks it's important to LOC the BUFG and BUFGCE such that you get the best dedicated routing for both buffers.

 

If you have trouble finding a single output of a DCM that can satisfactorily drive two such buffers, another approach would be to use a PLL, which can have multiple outputs generating the same clock frequency and phase.  Then you can have two outputs drive the two clock buffers.  Note that this adds some uncertainty to the timing between the two clock signals and can therefore add to the worst case skew.  However it may still be better than using one clock buffer with dedicated routing and another with less optimal routing.

-- Gabor
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