10-10-2013 11:49 AM
I have an emulation project where I have a DUT that is meant to operate at 'x' Mhz (10 Mhz). There is a wrapper around this DUT which is feeding/collecting data at '2x' Mhz (20 Mhz).
I want to have the ability to start and stop clock ticks to the DUT, (this is a requirement). So I am generating the clock signal for the DUT using an FSM. When I feed this clock directly to the DUT I run into timing issues.
Is there something I need to do to this generated user signal to make it a "clock signal" ?
10-10-2013 12:42 PM
It would be better if you wish to maintain a known relationship between the two clocks to use a single clock domain, routed on the global network, and control the submodule by using your FSM generated signal as a clock enable.
10-10-2013 01:12 PM
10-11-2013 05:49 AM
The Libraries guide for V6 describes the BUFGCE and BUFGCE_1 macros. It's usually possible to have a DCM output connect to more than one clock buffer component with high-speed dedicated routing. So for example your 10 MHz clock from a DCM could drive a BUFG for the constant clock as well as a BUFGCE for the clock to the DUT. The CE input of the BUFGCE would come from the output of a flip-flop clocked by the straight BUFG. In order to have low skew between the gated and non-gated clocks it's important to LOC the BUFG and BUFGCE such that you get the best dedicated routing for both buffers.
If you have trouble finding a single output of a DCM that can satisfactorily drive two such buffers, another approach would be to use a PLL, which can have multiple outputs generating the same clock frequency and phase. Then you can have two outputs drive the two clock buffers. Note that this adds some uncertainty to the timing between the two clock signals and can therefore add to the worst case skew. However it may still be better than using one clock buffer with dedicated routing and another with less optimal routing.