cancel
Showing results for 
Search instead for 
Did you mean: 
Observer
Observer
273 Views
Registered: ‎09-30-2016

Carry Chain Delay in Zynq UltraScale+ MPSoC

I implemented a carry chain and try to determine the delay from CI to CO[7] as well as between different carry8 elements. However when I implement the design and then run the timing report, I get values which seem to be way to high.

Anmerkung 2020-01-24 175227.png

Are these values for the propagation delay from CI to CO[7] really correct, and why do they differ between two adjustent carry8 elements?

I am using the FPGA xczu7ev-ffvc1156-2-e.

0 Kudos