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Explorer
Explorer
8,187 Views
Registered: ‎07-04-2014

Clk not found in timing constraint

Hi all,

 

I have a standard clk wizard module with different output clock speeds. Like that :

 

clk_wiz_0 I_clk_gen(
        .clk_in1        (EXT_CLK100M),
        .clk_40MHz_out   (),
        .clk_25MHz_out   (WB_clk),
        .clk_60MHz_out   (CAN_clk),
        .CLK_100M_BUFG   (CLK_100M_BUFG),
          // Status and control signals
        .reset          (1'b0),
        .locked         (I_PLL_LOCKED)      // output locked
           
    );

 

Then, I want to create clock names for those in my .xdc file to constraint input and output pin.

 

For example, If I do something like that :

create_clock -period 25.000 -name 40MHzClk -waveform {0.000 12.500} [get_nets I_clk_gen/clk_40MHz_out]

I get the following error message [Vivado 12-507] No nets matched 'I_clk_gen/clk_60MHz_out'.

 

Why is it not finding my clock? I_clk_gen is called in the top module.

 

 

 

 

 

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Xilinx Employee
Xilinx Employee
8,178 Views
Registered: ‎08-01-2008

Re: Clk not found in timing constraint


check these links
http://www.xilinx.com/support/answers/54799.html
https://forums.xilinx.com/t5/Synthesis/quot-Vivado-12-507-No-nets-matched-quot-warning-during-Synthesis/td-p/387779

you may share you code to run locally
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
8,172 Views
Registered: ‎04-16-2012

Re: Clk not found in timing constraint

Hi @bareil76

 

Try this constraint:

create_clock -period 25.000 -name 40MHzClk -waveform {0.000 12.500} [get_pins I_clk_gen/clk_40MHz_out]

 

 

You have to get_pins since I_clk_gen/clk_40MHz_out is an output of pin of clocking wizard and not a net.

 

Thanks,

Vinay

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Xilinx Employee
Xilinx Employee
8,164 Views
Registered: ‎09-20-2012

Re: Clk not found in timing constraint

Hi @bareil76

 

Open synthesized design and check if the net name specified in the constraint is correct or not in schematic view.

 

You need to specify period constraint only on MMCM input, tool auto propagates the clock to MMCM outputs.

 

If you want to rename tool generated clocks then use the technique mentioned in page-82 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug903-vivado-using-constraints.pdf 

Thanks,
Deepika.
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Explorer
Explorer
8,150 Views
Registered: ‎07-04-2014

Re: Clk not found in timing constraint

Thanks all

 

I have use create_generated_clock instead of create_clock.

 

Now for the 25MHz clock I have : 

 

 

create_generated_clock -name WB_SCLK [get_pins I_clk_gen/inst/mmcm_adv_inst/CLKOUT1]

and the warning disappears.

 

 

However, if I do the following :

 

create_generated_clock -name ADC_SCLK -source [get_pins I_clk_gen/inst/mmcm_adv_inst/CLKOUT1] -divide_by 4 [list [get_pins I_adc_top_hdmi/genblk1[0].I_adc_ctrl/SPI_SCLK_O] 
[get_pins {{I_adc_top_onBoard/genblk1[0].I_adc_ctrl/SPI_SCLK_O} {I_adc_top_onBoard/genblk1[1].I_adc_ctrl/SPI_SCLK_O} {I_adc_top_onBoard/genblk1[2].I_adc_ctrl/SPI_SCLK_O} {I_adc_top_onBoard/genblk1[3].I_adc_ctrl/SPI_SCLK_O}}]]

To generate an SPI clock it fails.

 

I have many instantiation of the same spi module. I want to constraint the spi clock of all the modules. Do I need to create a clock under a different names for each?

 

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Xilinx Employee
Xilinx Employee
8,140 Views
Registered: ‎04-16-2012

Re: Clk not found in timing constraint

Hi @bareil76

 

Yes, you have to create a clock with different names for each SPI clock.

 

Thanks,

Vinay

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Explorer
Explorer
8,127 Views
Registered: ‎07-04-2014

Re: Clk not found in timing constraint

OMG... ok thanks! I'll get to copy/paste right away!

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Guide
Guide
8,121 Views
Registered: ‎01-23-2009

Re: Clk not found in timing constraint

Do I need to create a clock under a different names for each?

 

Technically no - it is legal to have a single clock (whether primary or generated) attached to multiple design objects (although it might be good form to have a different one for each SPI) - but it shouldn't be illegal to do what you did.

 

What error message did you get?

 

Avrum

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Explorer
Explorer
7,878 Views
Registered: ‎07-04-2014

Re: Clk not found in timing constraint

Hi,

 

it was not an error, but a warning telling me that I had multiple sources for the same clock

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Guide
Guide
7,863 Views
Registered: ‎01-23-2009

Re: Clk not found in timing constraint

A warning is there to tell you about something that "may not be right" - in this case, it is, so you can ignore the warning. You can even demote the warning on this particular clock using the set_msg_config command (and you can use both the warning number and a wildcard string that will match just this message).

 

It is also acceptable to leave a clock unnamed. So for example if you have a scoped XDC file that constrains multiple instances of the SPI block, and each needs the generated clock, then you can create the clock without a name (to prevent clock name collisions). Even without a name, you can always get a clock object from the database using

 

get_clocks -of_objects [get_pins I_adc_top_onBoard/genblk1[0].I_adc_ctrl/SPI_SCLK_O]

 

Avrum

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Explorer
Explorer
5,062 Views
Registered: ‎07-04-2014

Re: Clk not found in timing constraint

Ohh!! Good to know. 

 

Thanks!

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