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Advisor
Advisor
8,839 Views
Registered: ‎02-12-2013

Clock Crossing Guide?

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Hello Guys,

 

I am searching for a Xilinx document that describes the standard ways to do clock domain crossing.   The clocks are very simple in the design I am currently implementing but this job requires that clock domain crossing be documented for review.  Rather than creating detailed explanations of how I will implement the few simple crossings in my design I want to be able to reference a Xilinx document and say I am using that technique.  I am hoping that Xilinx professionally written documentation describing standard techniques will better satisfy the kibitzers.

 

Is there a Xilinx document that describes the recommended clock crossing techniques?

 

    Pete

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DSP in hardware and software
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Re: Clock Crossing Guide?

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Maybe some other Xilinx folks will chime in with a Xilinx-published document that I'm not thinking of... but this is one of my favorites on the subject:

http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf

www.xilinx.com

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Re: Clock Crossing Guide?

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Hello @pedro_uno,

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug903-vivado-using-constraints.pdf (Chapter #6)

Regards,
Ashish
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Advisor
Advisor
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Registered: ‎02-12-2013

Re: Clock Crossing Guide?

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That reference describes the constraints for clock domain crosssing, good stuff, but I am looking for descriptions of actual clock crossing techniques.

 

For example, I have two clocks running at the same frequency but with unknown phase relationship.  It is common to use a shallow fifo to move data between the two domains.  It would be nice to reference a Xilinx document that describes that technique and others.

 

I looked in the "Ultrafast Methodology Guide" but did not find anything on the subject.

 

I think I know how to do clock crossing. I just wanted to reference Xilinx documentation on the subject since it tends be very good quality, at least compared to my ppt slides.

 

  Pete

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DSP in hardware and software
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Guide
Guide
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Registered: ‎01-23-2009

Re: Clock Crossing Guide?

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Pete,

 

I don't think there is any Xilinx documentation on this.

 

Some of this material is covered in the Xilinx class UltraFast Design Methodology class (as well as the Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users class) - particularly in the Appendix material.

 

You may be able to find information on the web, since clock crossing issues (and techniques) are not specific to FPGA technology...

 

Avrum

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Re: Clock Crossing Guide?

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Maybe some other Xilinx folks will chime in with a Xilinx-published document that I'm not thinking of... but this is one of my favorites on the subject:

http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf

www.xilinx.com

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Advisor
Advisor
8,523 Views
Registered: ‎02-12-2013

Re: Clock Crossing Guide?

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That is a very good reference.  In my case, the data crossing is 70 bits wide so I used the fifo technique described in section

 

    5.8.1 Multi-bit CDC signal passing using asynchronous FIFOS

 

In Xilinx FPGAs distributed memory fifos ar pretty cheap per bit. 

 

Thanks for the replies.

 

  Pete

 

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DSP in hardware and software
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