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bbergenf
Visitor
Visitor
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Registered: ‎04-02-2009

Clock Derived from Another Clock - How to constrain clock

I have in my design a clock that comes out of a DCM. This clock is called fclk. This clock feeds a FF that divides the clock by 2. I have created a constraint on the refclock input to the DCM. I understand the ISE automatically will derive a constraint on the fclk that comes out of the DCM. That is fine. But does ISE know how to constrain the half clock that comes out of the clock divider? Does it understand that there is a timing relationship between these two clocks, fclk and halfclock? If ISE does not automatically generate constraints on halfclock,  what is the syntax for constraining it in the UCF file?

 

I have read the constraints guide but it is not clear on this issue.

 

Thanks,

Bruce

Bruce Bergenfeld
Synterix Technology Ltd.
www.synterix.com
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3 Replies
bassman59
Historian
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Registered: ‎02-25-2008


bbergenf wrote:

I have in my design a clock that comes out of a DCM. This clock is called fclk. This clock feeds a FF that divides the clock by 2. I have created a constraint on the refclock input to the DCM. I understand the ISE automatically will derive a constraint on the fclk that comes out of the DCM. That is fine. But does ISE know how to constrain the half clock that comes out of the clock divider? Does it understand that there is a timing relationship between these two clocks, fclk and halfclock? If ISE does not automatically generate constraints on halfclock,  what is the syntax for constraining it in the UCF file?

 

I have read the constraints guide but it is not clear on this issue.

 

Thanks,

Bruce


The tools won't automagically know that the signal you divide in the flip-flop is a clock that has any relationship to anything else.

 

Two things:

 

a) you might need to put a BUFG on the output of your divider flip-flop, as the tools may not do so automatically.

 

b) In your UCF, create a PERIOD constraint on the divided clock net. If there's a BUFG on the net, the constraints editor will see it and realize that the signal is a clock and will allow you to place the PERIOD constraint.

 

Note, though, that since the divided clock comes from a flip-flop, it will have some clock-to-out delay from the fast clock, if that is important for your application.

 

-a

----------------------------Yes, I do this for a living.
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ywu
Xilinx Employee
Xilinx Employee
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Registered: ‎11-28-2007

A couple of subtleties:

 

A signal driven by BUFG doesn't automatically make it a clock. The tool recognizes a clock only when you use the signal as a clock (e.g. driving clock input of an FF).

 

When you use a clock generated from the logic, there are more delays (routing from the FF output to BUFG, BUFG delay, global clock routing delay) than just the clock-to-out you need to consider if that is important.You should avoid using this kind of clock if all possible.

 

Cheers,

Jim

Message Edited by jimwu on 04-03-2009 06:57 AM
Cheers,
Jim
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horkel
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Registered: ‎05-31-2009

Look in XAPP132 how to get divided (and multiplied) clocks from DLL.

 

The advantage is that the phase of derived clock is well defined and may be changed if needed by DLL configuration (directly from VHDL). The timing constraint for the derived clock is generated automatically by ISE (including phase shift if used).

 

Milan

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