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Registered: ‎09-18-2018

Clock Mux special case

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I am trying to constrain a clock manager module with architecture shown below:

clock_manager.png

All three output clocks at the bottom of the diagram will be used in the design, and all will be interacting with each other at some point. That means that I will have a clock from a clock mux interacting with the feeder clock. According to this post: https://forums.xilinx.com/t5/Timing-Analysis/Timing-constraints-for-multiplexed-clocks/m-p/981270#M16978 the solution says at the end that a more complex set of constraints is required for this case. What is this more complex set?

In UG949 talks about this some in the section about overlapping clocks driven by a clock multiplexer. Is this the solution? I don’t want it to set a false path between my 50 and 150MHz clock. I want to constrain that my own way. Also, in UG949, they create a generated clock. But elsewhere, Xilinx says these will already be generated…

Any help would be much appreciated.

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Moderator
Moderator
616 Views
Registered: ‎01-16-2013

Let me try to explain a bit as per your clocking topology what we need to consider while constraining the same.

 

PLL with external clock (PLL1) and PLL with board clock (PLL2).

The 300MHz clocks from PLL1 and PLL2 looks like synchronous but practically the phase is unknown and hence asynchronous.

So if there is any interaction between 300MHz clock generated from PLL1 and PLL2 need to be managed as per async cdc.

 

BUFGMUX: You need to have generated clock constraint on the output of BUFGMUX and then you need to provide the exception constraints for them. Refer AR https://www.xilinx.com/support/answers/59484.html

 

If PLL2 (300MHz) clock is active at BUFGMUX then all other clocks downwards are synchronous. And you can have multi-cycle constraint to adjust the edge alignment for calculation and relaxation.

 

The confusion will arise when PLL1 clock is active at BUFGMUX then 50MHz clock will be under async relationship with rest of the clock (except 300MHz clock of PLL2). So you need to manage that again with set of constraints.

 

I hope the above details will be helpful to constraint the clocking topology.

 

Thanks,
Yash

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2 Replies
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Adventurer
Adventurer
648 Views
Registered: ‎05-30-2017

See avrumw's second reply HERE.

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Highlighted
Moderator
Moderator
617 Views
Registered: ‎01-16-2013

Let me try to explain a bit as per your clocking topology what we need to consider while constraining the same.

 

PLL with external clock (PLL1) and PLL with board clock (PLL2).

The 300MHz clocks from PLL1 and PLL2 looks like synchronous but practically the phase is unknown and hence asynchronous.

So if there is any interaction between 300MHz clock generated from PLL1 and PLL2 need to be managed as per async cdc.

 

BUFGMUX: You need to have generated clock constraint on the output of BUFGMUX and then you need to provide the exception constraints for them. Refer AR https://www.xilinx.com/support/answers/59484.html

 

If PLL2 (300MHz) clock is active at BUFGMUX then all other clocks downwards are synchronous. And you can have multi-cycle constraint to adjust the edge alignment for calculation and relaxation.

 

The confusion will arise when PLL1 clock is active at BUFGMUX then 50MHz clock will be under async relationship with rest of the clock (except 300MHz clock of PLL2). So you need to manage that again with set of constraints.

 

I hope the above details will be helpful to constraint the clocking topology.

 

Thanks,
Yash

View solution in original post