UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor goodlinr
Visitor
487 Views
Registered: ‎02-20-2018

Clock Replication and Constraints

Jump to solution

I'm working on updating the way we handle timing constraints and have run into a scenario that I think needs some work.

We have a large design that uses several clocks: 200MHz, 125MHz, 50MHz, FPGA_MHz.

  - The custom PCB has a 200MHz oscillator brought into a pin and there is another external connection to the FPGA_MHz clock source.  The 200MHz is used as the input clock to a Clocking Wizard (MMCM primitive is used) and then the outputs of it are 200MHz, 125MHz and 50MHz.  The FPGA_MHz source is also fed into a similar Clocking Wizard IP and the output is a clock at the same speed.  Note that both external inputs are differential and the IP is used to convert from differential to single ended.

After reading some other posts I am working on the strategy to create the timing constraints where I create two XDC files: 

  - The first XDC file (let's call it fileOne.xdc) only contains the external port clocks (200MHz and FPGA_MHz) and here are a couple lines from the file:

        create_clock -period 5.000 -name SYSCLK_P -waveform {0.000 2.5} -add [get_ports SYSCLK_P]
         create_clock -period 9.000 -name CLK_EXT_P -waveform {0.000 4.500} -add [get_ports CLK_EXT_P]

    - Note that the SYSCLK_P is the 200MHz source and CLK_EXT_P is the FPGA_MHz source (it's 111.11 MHz in this case).

    - This XDC is used in both synthesis and implementation

  - The other XDC file (let's call it fileTwo.xdc) is generated from the synthesized design.  It contains constraints for CDCs which I have created based on this post: https://forums.xilinx.com/t5/Timing-Analysis/how-to-constrain-a-CDC/td-p/748174 I am able to generate bitstreams with no timing errors (my builds take about 30 minutes to synthesize and 2 hours to implement on a xc7k410). 

    - This file is created using get_clocks with the synthesized design open to then use create_clock (none of the clocks in fileTwo.xdc are the same clocks from fileOne.xdc).

    - Here are a few lines from fileTwo.xdc

        create_clock -period 5.000 -name clkfbout_CLOCK_GEN_200_MHz -waveform {0.000 2.500}
          create_clock -period 5.000 -name OUT_200_MHz_CLOCK_GEN_200_MHz -waveform {0.000 2.500}
          create_clock -period 8.000 -name OUT_125_MHz_CLOCK_GEN_200_MHz -waveform {0.000 4.000}
          create_clock -period 20.000 -name OUT_50_MHz_CLOCK_GEN_200_MHz -waveform {0.000 10.000}
          create_clock -period 9.000 -name clkfbout_CLOCK_GEN_SINGLE_ENDED_111 -waveform {0.000 4.500}
          create_clock -period 9.000 -name CLOCK_OUT_111_CLOCK_GEN_SINGLE_ENDED_111 -waveform {0.000 4.500}
          create_clock -period 9.000 -name clkfbout_CLOCK_GEN_SINGLE_ENDED_111_1 -waveform {0.000 4.500}
          create_clock -period 9.000 -name CLOCK_OUT_111_CLOCK_GEN_SINGLE_ENDED_111_1 -waveform {0.000 4.500}
          create_clock -period 9.000 -name clkfbout_CLOCK_GEN_SINGLE_ENDED_111_2 -waveform {0.000 4.500}
          create_clock -period 9.000 -name CLOCK_OUT_111_CLOCK_GEN_SINGLE_ENDED_111_2 -waveform {0.000 4.500}
          create_clock -period 9.000 -name clkfbout_CLOCK_GEN_SINGLE_ENDED_111_3 -waveform {0.000 4.500}
          create_clock -period 9.000 -name CLOCK_OUT_111_CLOCK_GEN_SINGLE_ENDED_111_3 -waveform {0.000 4.500}
          create_clock -period 9.000 -name clkfbout_CLOCK_GEN_SINGLE_ENDED_111_4 -waveform {0.000 4.500}
          create_clock -period 9.000 -name CLOCK_OUT_111_CLOCK_GEN_SINGLE_ENDED_111_4 -waveform {0.000 4.500}
          set_max_delay -datapath_only -from [get_cells -hier] -to [get_clocks OUT_125_MHz_CLOCK_GEN_200_MHz] 7.9
          set_max_delay -datapath_only -from [get_cells -hier] -to [get_clocks OUT_50_MHz_CLOCK_GEN_200_MHz] 19.9
          set_max_delay -datapath_only -from [get_cells -hier] -to [get_clocks OUT_X1_CLOCK_GEN_SYSTEM_COHERENT_111] 8.900
          set_max_delay -datapath_only -from [get_clocks OUT_125_MHz_CLOCK_GEN_200_MHz] -to [get_clocks OUT_X1_CLOCK_GEN_SYSTEM_COHERENT_111] 7.9
          set_max_delay -datapath_only -from [get_clocks OUT_X1_CLOCK_GEN_SYSTEM_COHERENT_111] -to [get_clocks OUT_125_MHz_CLOCK_GEN_200_MHz] 7.9

    - I have a Clocking Wizard called CLOCK_GEN_200_MHz, CLOCK_GEN_SYSTEM_COHERENT_111 and CLOCK_GEN_SINGLE_ENDED_111

    - fileTwo.xdc is used only in implementation (this strategy of two XDCs with one in synthesis and implementation and the other in implementation only is what I found in another post...but I cannot find it at this time)

 

My questions are this:

1. What are those clocks that look like duplicate copies of output clocks from my Clocking Wizards (in the green font with the '_1', '_2', '_3', etc)? Can I get rid of them or handle them differently?

2. Should I be using create_generated_clock instead of create_clock for any/all of the clocks in fileTwo.xdc? If so, I'm confused on the syntax I should use.  Would this be correct for one of them?

    create_generated_clock -name CLOCK_OUT_111_CLOCK_GEN_SINGLE_ENDED_111 -source CLOCK_OUT_111_CLOCK_GEN_SINGLE_ENDED_111_1

    ...this does not seem right to me, but I'm not sure what else it would be.

I'm using Vivado 2018.3 and just switched over to using it (was using 2015.4.1)

Thank you in advance!

 

0 Kudos
1 Solution

Accepted Solutions
Visitor goodlinr
Visitor
369 Views
Registered: ‎02-20-2018

Re: Clock Replication and Constraints

Jump to solution

At this point my previous post is looking good.

In summary here is what I did:

  - I only use a single XDC file for timing constraints.  It contains clock definitions for the external clocks coming in on pins to the FPGA. I know what those are based on the hardware design of our system and can create the constraints before synthesis.

  - I let the tools handle constraining the auto-generated clocks and have no manually created constraints for them in my XDC file.

  - I now know how to predict what the auto-generated clocks will be (see the previous post) and can create my CDC constraints before synthesis (see links to other posts earlier in the thread for doing this).

I have been able to generate bitstreams with no timing errors and I do not have to open the synthesized design like I was trying to do earlier.  Thus time saved :)

Thanks @drjohnsmith for your help in figuring this out!

8 Replies
Scholar drjohnsmith
Scholar
468 Views
Registered: ‎07-09-2009

Re: Clock Replication and Constraints

Jump to solution

Can you enlighten us please as to why you want two XDC files, and have different for synthesis and implimentation ?

As i underatand things,  clocks out of the clock IP , will have constraints automaticlay generate by the tools based upon the clock constraints of their inputs.

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Visitor goodlinr
Visitor
460 Views
Registered: ‎02-20-2018

Re: Clock Replication and Constraints

Jump to solution

I'm trying to use two XDC files as I was trying to do what avrumw suggests in this post:

https://forums.xilinx.com/t5/Synthesis/Vivado-auto-derived-or-IP-clocks-not-found-when-parsing-XDC/td-p/797487

I was having a similar issue as what the original post in that thread was discussing.  This is the post I alluded to earlier that I couldn't find - thankfully I found it.

 

Also, in looking for this I came across this discussion which may help me:

https://forums.xilinx.com/t5/Vivado-TCL-Community/TCL-XDC-Renaming-clocks/m-p/450884#M1424

 

Does this seem like what I need?

Thanks!

0 Kudos
Scholar drjohnsmith
Scholar
442 Views
Registered: ‎07-09-2009

Re: Clock Replication and Constraints

Jump to solution

@avrumw is very knowledgable on these things,

   much more thna me,

 

he does say though, another optoin ,  ... is to  use two files.

 

That to me says, don't unless you need to,

     his first way is I understand to let the tools work, don't use two files,

 

What errors are you seeing with a single file that your tryign to fix with two ?

 

KISS is my policy, the more patches oen adds the more chance of them interacting and being wrong..

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Visitor goodlinr
Visitor
437 Views
Registered: ‎02-20-2018

Re: Clock Replication and Constraints

Jump to solution

I definitely agree with the KISS strategy @drjohnsmith 

My original problem was that I was getting a bad timing score.  Then I pursued how to better constrain my CDCs (I was previously just declaring all clocks asynchronous which @avrumw has stated is a bad technique.  So in trying to constrain my CDCs as described in the post I already referenced I had to figure out how to know which clocks are present in my design.  I could not figure out how to wrangle those '_1', '_2', etc (possibly derived or duplicated clocks?) to a state which I could predict which ones would be present (I have multiple projects I'm working that are all similar, but different).  So I found the post about using the synthesized design with get_clocks to determine what clocks are present in the design.  I'm using TCL scripts with Vivado in Project Mode to launch synthesis, then open the design, generate fileTwo.xdc using TCL scripts, then run implementation.

I would love to not have to open the synthesized design and generate an XDC file (this takes quite a bit of time to open up as my design is pretty big), but I don't know how to prevent those derived/duplicated clocks from appearing.  Any ideas? How can I make one constraints file before synthesis that will be sufficient in this situation?

I have also recently found (as I was tracking down another issue unrelated to this) that there is a setting in Synthesis called '-bufg' which one of the users recommends setting that value to 0 and explicitly inserting any needed BUFGs that are required.  Currently my '-bufg' setting has a value of 12 (I'm assuming this is the Vivado default).  Does this setting have anything to do with these derived/duplicated clocks?

Also, I've been using the terms: derived/duplicated clocks...but if this is incorrect terminology please let me know what the right terms are so I can be more clear and continue to try to find the answer elsewhere as well.

Thanks!

Visitor goodlinr
Visitor
430 Views
Registered: ‎02-20-2018

Re: Clock Replication and Constraints

Jump to solution

Some additional information that I found:

  This is from UG903 pg 67:

       Name Conflicts
       In case of name conflict between two auto-generated clocks, the Vivado IDE adds unique
       suffixes to differentiate them, such as:
        • usrclk
        • usrclk_1
        • usrclk_2
        • ...
       To force the name of the generated clocks:
        • Choose unique and relevant net names in the RTL, or
        • Use create_generated_clock to explicitly define the generated clock constraints.

  From this it appears the reason I'm getting these other '_1','_2' clocks is because there is a "Name Conflict" in the auto-generated clocks that Vivado is producing. 

It seems the answer to my original question is that this to use create_generated_clock instead of create_clock.  I'll try some attempts at using this command.

 

Now the question is why is Vivado auto-generating these clocks? Is there a way I can prevent this, or is this to be expected?  Is there a specific name to use when renaming these clocks?  I was thinking I could rename them to the original name (without the '_1' for example) but that seems like it will not work because it will just result in a name conflict.  Does anyone have a convention of method they use for renaming these?

Scholar drjohnsmith
Scholar
420 Views
Registered: ‎07-09-2009

Re: Clock Replication and Constraints

Jump to solution
why do you not want to let the tools derive clock constraints for you ?

as for clock crossing,
You have the correct circuit in place to handle that ? Why do you think cross clock is bad ?


BTW: as for time,when you get into days to synth and implement, then you have a big design,
but I know what you mean, I have a design here that takes 13 minutes to synthesis, just to long to wait, but to short to do anything much else,,,


<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Visitor goodlinr
Visitor
418 Views
Registered: ‎02-20-2018

Re: Clock Replication and Constraints

Jump to solution

I'm leaning toward letting the tools create my constraints for me on these auto-generated clocks.  I thought I had to manually constrain them, but it seems that is not the case.  I'm working on a build with letting the tools constrain them now.  Keep reading below for some progress I've made.

As for the CDCing, I know my CDC VHDL modules work, it's just the timing constraints for them that I'm dealing with now.  The timing constraints for them are working fine at this point, but I'm trying to eliminate any superfluous clocks that I've created with this 'create_clock' command in the original post.  I'm also trying to determine how to figure out what my clocks are named so I can create those CDC constraints (preferably before I even run synthesis).  Maybe this answers your question @drjohnsmith ?

Now, onto some progress I've made...here's my thoughts:

I was able to determine that the reason the name conflicts are generated is because I actually have a Clocking Wizard instantiated in an entity that I have multiple copies of.  For example, I have a hierarchy like this:

  - toplevel

    - inst_thing_0

    - inst_thing_1

    - inst_thing_2

  where 'inst_thing' is an entity and is instantiated 3 times.  There is a Clocking Wizard inside this module and that Clocking Wizard is the one where the auto-generated clocks experience a naming conflict.  Using TCL and the tip in the UG903 pg 67 I can use the [get_clocks -of_objects <pin/net/port>] to rename these outputs with meaningful names. Yay!

Also, now that I know how to rename these and expect what the names will be, I can setup my constraints before synthesis so I no longer need to open the synthesized design in order to determine what all of the clocks will be. Yay!

...this is in theory anyway. I'm working on setting up the build now and I'll post again when I have some success or failure with this.

Thanks!

Visitor goodlinr
Visitor
370 Views
Registered: ‎02-20-2018

Re: Clock Replication and Constraints

Jump to solution

At this point my previous post is looking good.

In summary here is what I did:

  - I only use a single XDC file for timing constraints.  It contains clock definitions for the external clocks coming in on pins to the FPGA. I know what those are based on the hardware design of our system and can create the constraints before synthesis.

  - I let the tools handle constraining the auto-generated clocks and have no manually created constraints for them in my XDC file.

  - I now know how to predict what the auto-generated clocks will be (see the previous post) and can create my CDC constraints before synthesis (see links to other posts earlier in the thread for doing this).

I have been able to generate bitstreams with no timing errors and I do not have to open the synthesized design like I was trying to do earlier.  Thus time saved :)

Thanks @drjohnsmith for your help in figuring this out!