02-06-2021 10:38 PM
I am trying to figure out how to understand the delay time from Clock-caple Clock Input to Output with pll/mmcm. According to the Kintex-7 FPGAs Data Sheet:DC and AC Switching characteristics(DS182,p50). TICKOFPLLCC/TICKOFMMCMCC is less than 1ns. But Clock-caple Clock Input to output delay without MMCM/pll TICKOF is more than 7ns. How to explain the delay time would decrease by using pll/mmcm
02-07-2021 03:14 AM
Hi @lilia20190227 ,
CLKFB pin is sourced from BUFH.
As mentioned on UG472, BUFHs have the ability to serve as a feedback to the MMCM/PLL and the clock insertion delay can be compensated for.
I hope this would help.
02-07-2021 03:49 AM
The MMCM / PLL , adds to the delay of the clock,
which assuming your clock is constant, which it has to be for the MMCM / Pll to work properly
solves the delay problem to the inputs,
So if your clock period was 10 ns, and the internal delay was 7 ns,
by adding 3ns, the internal and external clocks are aligned.
The way t does this is to use the feedback loop as the reference to compare against the input.
What it sound like you are doing is feeding the clock in, then feeding it out the chip,
thus you are suffering two things , internal delays and moving a clock net to slower local routing,
If you want to test the clock to out,
define a DDR ,ensure its in the IOB register, feed the clock from the MMCM.PLL to the clock of the DDR< and output, and tie the two inputs tot he DDR to 1 and 0 respectively.
This will generate a clock out at half the period of the MMCM / PLL clock,
If you really want a clock out sync to the input clock,
feed the clocking wizard with the DDR output outside the FPGA,
These are old but could be of interest