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Visitor
Visitor
1,287 Views
Registered: ‎06-01-2015

Clock domain tutorial

Hello,

could someone point me to documentation about multiple clock domain design ? I'm discovering the concept !

 

I'm a beginner, I did some things with a spartan3, basic examples in vhdl, but always with a single clock at 50MHz on the board.

I read that the ram and the multipliers on that fpga could run above 250MHz.

 

How can I create a module (using ram and mult) running at 100MHz with other modules running at 50MHz ?

Any simple VHDL code ?

 

Thank you

 

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Moderator
Moderator
1,279 Views
Registered: ‎09-15-2016

Hi @raiatea

 

Check this document:

https://www.ece.ucsb.edu/its/bluespec/training/BSV/slides/Lec10_Multiple_Clocks.pdf

 

Regards

Rohit

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Regards
Rohit
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Visitor
Visitor
1,261 Views
Registered: ‎06-01-2015

Thank you for the link. Multiple clocks looks widely used in SoCs, but I can't find clear examples.

I looked too at the Timing Closure User Guide ug612, p157

 

I'm thinking about the following :

 

 - use the board clock at 50MHz and a PLL to generate clk0 at 50MHz, and clk2x at 100MHz

 - use clk0 for the modules at 50MHz and clk2x for the module at 100MHz

 - use a synchronous FIFO for crossing the domains

 

Any link to a code example in ISE, Vivado, university program, workshop,

or a book chapter about multiple clock design on FPGA ?

 

Regards

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Teacher
Teacher
1,239 Views
Registered: ‎07-09-2009

or you could run everything at 100 mhz, and a clock enable for the slower part of the circuit.

 

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